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參數(shù)資料
| 型號： | TTSI1K16T3TL |
| 英文描述： | 1024-Channel, 16-Highway Time-Slot Interchanger |
| 中文描述： | 1024通道，16道時隙交換器 |
| 文件頁數(shù)： | 36/64頁 |
| 文件大?。?/td> | 1110K |
| 代理商： | TTSI1K16T3TL |
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TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
36
Lucent Technologies Inc.
Configuration Register Architecture
Note
: All registers’ bits default to 0 upon reset, unless noted otherwise.
All TDM highway data, which is stored in the TSI, will have the following convention. Bit 7 is first transmitted
and first received; bit zero is last transmitted and last received. This convention applies to the data read from
the data store, the host data transmitted via the connection store, and any other configuration register which
stores highway data, such as the idle code registers and the test-pattern generator data register.
Table 15. General Command Register (0x00)
Bit
7
Symbol
CSV
Name/Description
Chip Select Valid.
This bit is valid while the TTSI1K16T is in synchronous micropro-
cessor interface mode only. When this bit is programmed to be 1, the chip select input
pin is sampled when AS is active. When 0, chip select is latched one PCLK after AS is
active.
External Drivers.
Used to select the use of external drivers on transmit highways. A 0
indicates that no external buffers are being used; therefore, the TXD pins will become
3-stated for time slots that are programmed as such. A 1 indicates that the TXD output
highways are connected to external drivers; thus, the TXD pins will always be driven
to prevent floating nodes at the inputs of the external drivers. The TXOE[0—15] out-
puts always reflect the high-impedance status of the corresponding TXD[0—15] high-
ways, regardless of the ED bit setting. The only exception to this is when TEST is
asserted, which 3-states all outputs.
6
ED
See Table 41, Transmit Highway 3-State Options, on page 49 for other methods of
3-stating the transmit highways.
Reserved.
Read as 0.
Interrupt Output Enable.
This bit, when set to a 1, enables the INT output signal to
be driven based on the status of the internal interrupts and their corresponding individ-
ual mask bits. When 0, the output will remain 3-stated.
Interrupt Polarity.
This bit defines the polarity of INT, as output from the TTSI1K16T.
A 1 selects an active-low interrupt output (INT). A 0 selects an active-high interrupt
output (INT), and is the default polarity.
Frame Sync Polarity.
This bit defines the polarity of FSYNC, as sampled by CK,
which designates the beginning of the frame. A 1 selects an active-high frame syn-
chronization (FSYNC). A 0 selects an active-low frame synchronization (FSYNC).
Frame Sync Sample Edge.
This bit selects the clock edge of the CK input that is
used to sample the frame synchronization input. A 1 selects the rising edge; and a 0
selects the falling edge of CK.
Global Transmit Enable.
When 0, all 16 transmit highways are 3-stated. GXE
defaults to 0 so that all outputs can be held in a high-impedance state until they have
been configured and individually enabled.
5
4
—
INTOE
3
INTP
2
FSP
1
FSSE
0
GXE
For other methods of 3-stating transmit highways, see Table 41, Transmit Highway
3-State Options, on page 49.
相關(guān)PDF資料 |
PDF描述 |
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| TTSI1K16T | 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時隙交換機) |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 2048-Channel, 32-Highway Time-Slot Interchanger |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TTSI1K16T3TL-DB | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| TTSI2K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
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