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參數(shù)資料
| 型號： | TTSI1K16T3TL |
| 英文描述： | 1024-Channel, 16-Highway Time-Slot Interchanger |
| 中文描述： | 1024通道，16道時隙交換器 |
| 文件頁數(shù)： | 11/64頁 |
| 文件大?。?/td> | 1110K |
| 代理商： | TTSI1K16T3TL |
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Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
11
Lucent Technologies Inc.
Pin Information
(continued)
Table 4. TTSI1K16T Pin Descriptions
(continued)
*I
u
indicates internal 100 k
pull-up resistor, and I
d
indicates 17.5 k
pull-down resistor.
Symbol
D[7—0]
Type
*
I/O
Description
Host Processor Data Bus.
These pins
provide an 8-bit, bidirectional data bus.
Read data is valid for one PCLK cycle
coincident with the assertion of DT. Write
data must be held throughout the
access.
Host Processor Address Bus.
A14—A0 must remain valid throughout the entire
processor access. A0 is the least significant address signal and is used to select
byte locations.
Read/Write.
This signal indicates a read or write cycle. Read cycle is indicated with
a logic 1; a write cycle is indicated with a logic 0.
Interrupt.
This pin will be asserted to indicate that an interrupt condition has
occurred. This output will remain active until the interrupt status register has been
cleared (read). The polarity of this output is controlled through the INTP bit (bit 3) of
the general command register. The default value of this register is 0, which indi-
cates active-high. This output is tristated until INTOE (bit 4) of the general command
register is set to 1. The polarity of this output should be selected before the pin is
enabled.
Receive Data Highways 0
—
15.
Serial TDM highways receiving data at rates of
2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s.
Frame Synchronization.
This signal indicates the beginning of a frame every
125
μ
s (8 kHz). FSYNC can be active-low or active-high, but its polarity is the same
for all highways. FSYNC can be sampled on a positive or negative CK edge. Time-
slot numbers and bit offsets are assigned relative to the detection of FSYNC. There
are no restrictions on the duty cycle of FSYNC as long as the setup and hold timing
requirements relative to CK are met.
Clock.
This input is the clock reference for all the transmit and receive highways. Its
frequency can be 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz. The fre-
quency selection for CK must be set equal to or greater than the fastest highway
data rate.
Clock Speed Select for CK Pin.
These strap pins indicate the frequency of CK:
Host Processor Data Bus.
These pins
provide an 8-bit, bidirectional data bus.
Write data must be valid for the duration
of DS. Read data is valid while DT is
asserted.
A[14—0]
I
R/W
I
INT
O
RXD[0—15]
I
u
FSYNC
I
CK
I
CKSPD[2—0]
I
CKSPD2
0
0
0
0
1
Transmit Data Highways 0—15.
Serial TDM highway transmitting data at rates of
2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. During external driver mode, the
TXD[0—15] outputs will be continuously driven. The only exception to this is when
the TEST input is asserted. When not in external driver mode, this highway can be
tristated on a per-time-slot basis.
CKSPD1
0
0
1
1
X
CKSPD0
0
1
0
1
X
CK (MHz)
2.048
4.096
8.192
16.384
Reserved
TXD[0—15]
O
See Table 41, Transmit Highway 3-State Options, on page 49 for a detailed descrip-
tion of all methods for 3-stating the transmit highways.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TTSI1K16T3TL-DB | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| TTSI2K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
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