參數(shù)資料
型號(hào)： TTSI1K16T3TL
英文描述： 1024-Channel, 16-Highway Time-Slot Interchanger
中文描述： 1024通道，16道時(shí)隙交換器
文件頁(yè)數(shù)： 41/64頁(yè)
文件大?。?/td> 1110K
代理商： TTSI1K16T3TL
Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
41
Lucent Technologies Inc.
Configuration Register Architecture
(continued)
Table 24. Test Command Register (0x09)
Bit
7
Symbol
STTPG
Name/Description
Start Test-Pattern Generator.
Writing a 1 to this register will cause the genera-
tor to start generating a test pattern based on the pattern indicated in the test-
pattern style register. Writing a 0 to this register will stop the test-pattern genera-
tion and provide the opportunity to change the test-pattern style.
Start Test-Pattern Checker.
Writing a 1 to this register will cause the checker to
start locking on to a test pattern based on the pattern indicated in the test-
pattern style register. Writing a 0 to this register will stop the test-pattern check-
ing and provide the opportunity to change the test-pattern style.
Test-Pattern Generator Highway Data Rate.
These bits are used to indicate
the highway data rate of the transmit highway selected for test-pattern genera-
tion. It must match the Tx highway data rate which was set in transmit highway
configuration register (byte 2), HDR[1—0] bits. The transmit highway selection
for test-pattern generation is done using the connection store. Only one highway
at a time can be involved with test-pattern generation. Test-pattern generation
and checking does not affect the operation of other time slots or highways.
6
STTPC
5—4
GENHDR
[1—0]
GENHDR1
0
0
1
1
Test-Pattern Checker Highway Data Rate.
These bits are used to indicate the
highway data rate of the receive highway selected for test-pattern checking. It
must match the Rx highway data rate which was set in receive highway configu-
ration register (byte 2), HDR[1—0] bits. The transmit highway selection for test-
pattern generation is done using the test-pattern checker highway register. Only
one highway at a time can be involved with test-pattern checking. Test-pattern
generation and checking does not affect the operation of other time slots or high-
ways.
GENHDR0
0
1
0
1
2.048 Mbits/s (default)
4.096 Mbits/s
8.192 Mbits/s
0.000 Mbits/s (idle, not transmitting data)
3—2
CHKHDR
[1—0]
CHKHDR1
0
0
1
1
Reserved.
Read as 0.
CHKHDR0
0
1
0
1
2.048 Mbits/s (default)
4.096 Mbits/s
8.192 Mbits/s
0.000 Mbits/s (idle, not receiving data)
1—0
—
相關(guān)PDF資料
PDF描述
TTSI1K16T 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時(shí)隙交換機(jī))
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
TTSI2K32T3BAL 2048-Channel, 32-Highway Time-Slot Interchanger
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時(shí)隙交換機(jī))
TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TTSI1K16T3TL-DB 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述:
TTSI2K32T 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger
TTSI2K32T3BAL 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger
TTSI4K32T 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger
TTSI4K32T3BAL 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger
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