參數(shù)資料
型號(hào)： TTSI1K16T3TL
英文描述： 1024-Channel, 16-Highway Time-Slot Interchanger
中文描述： 1024通道，16道時(shí)隙交換器
文件頁(yè)數(shù)： 48/64頁(yè)
文件大?。?/td> 1110K
代理商： TTSI1K16T3TL
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Preliminary Data Sheet
February 1999
48
Lucent Technologies Inc.
Configuration Register Architecture
(continued)
Table 39. Receive Highway Configuration Register (Byte 1) (0x1801 + 4i)
*
* i = the receive highway number.
Table 40. Receive Highway Configuration Register (Byte 2)
(0x1802 + 4i)
*
* i = the receive highway number.
Bit
7
6—0
Symbol
—
RTSOFF
[6—0]
Name/Description
Reserved.
Read as 0.
Receive Highway Time-Slot Offset[6
—
0].
RTSOFF is used to offset the begin-
ning of an incoming frame by the indicated number of time slots (bytes). If no
time-slot offsetting is required, these bits should be set to zero. The following
table shows the range of offsets for the different highway data rates.
Highway Data Rate Time-Slot Offset Range
2.048 Mbits/s 0—31
4.096 Mbits/s 0—63
8.192 Mbits/s 0—127
Note:
A time slot is always 8 bits. A bit period is relative to the highway data rate
set for each highway.
RTSOFF, RBITOFF, and RFBOFF are used in conjunction to define the start of
the incoming frame. The values are added together to position the sampling of
time slot 0, bit 0.
Bit
7—3
2
Symbol
—
LC
Name/Description
Reserved.
Read as 0.
Loopback Control.
This bit is used to control the internal loopback of the TXD
highway to the corresponding RXD highway. When set to 1, the TXD highway as
input to this RXD highway. The transmit highway involved will be internally
looped back to the matching receive highway so that the TXD[i] output is now the
input to RXD[i]. When a particular highway is in this mode, the receive highway
offset must be 1/2-bit greater than the corresponding transmit highway offset.
When LC is cleared to 0, the RXD pin is the source of highway data (default).
Receive Highway Data Rate[1—0].
HDR1
HDR0
0
0
2.048 Mbits/s (default)
0
1
4.096 Mbits/s
1
0
8.192 Mbits/s
1
1
0.000 Mbits/s (idle, not receiving data)
All of the receive highways are grouped into pairs. RXD0 with RXD1, RXD2 with
RXD3, . . . , and RXD14 with RXD15. The maximum combined bandwidth for
each pair is 8.192 Mbits/s. Refer to Table 6, Rx Highway Data Rate Options, on
page 18 for highway rate combination.
1—0
HDR[1—0]
相關(guān)PDF資料
PDF描述
TTSI1K16T 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時(shí)隙交換機(jī))
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger
TTSI2K32T3BAL 2048-Channel, 32-Highway Time-Slot Interchanger
TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時(shí)隙交換機(jī))
TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TTSI1K16T3TL-DB 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述:
TTSI2K32T 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger
TTSI2K32T3BAL 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger
TTSI4K32T 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger
TTSI4K32T3BAL 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger
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