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參數(shù)資料
| 型號： | TTSI1K16T3TL |
| 英文描述： | 1024-Channel, 16-Highway Time-Slot Interchanger |
| 中文描述： | 1024通道，16道時隙交換器 |
| 文件頁數(shù)： | 39/64頁 |
| 文件大?。?/td> | 1110K |
| 代理商： | TTSI1K16T3TL |
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Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
39
Lucent Technologies Inc.
Configuration Register Architecture
(continued)
Table 22. Interrupt Status Register
*
(0x07)
* Read-only register.
This register is clear on read. Once the status bits are read, they will remain cleared until the next interrupt event
occurs. The interrupt mask register in combination with the global interrupt enable GIE (bit 0) in the global interrupt
mask register determines when the INT pin gets asserted when an interrupt status bit gets set. In general, the
interrupt status register bits will update regardless of the mask bits. The exception to this is the FSERR bit, which
will not be set if the corresponding mask bit is set.
Bit
7
6
Symbol
—
FSERR
Name/Description
Reserved.
Read as 0.
Frame Sync Error.
When set to 1, this bit indicates that an error related to frame
sync has occurred. This error could be a result of a missing FSYNC or a mis-
aligned FSYNC.
Test Pattern Detected.
The TPD bit indicates the state of the test-pattern
checker. When TPD = 0, the test-pattern checker
has not
yet located the
selected test pattern. When TPD = 1, the test-pattern checker
has
located the
selected test pattern. Test-pattern data must be error-free for 32 time slots before
it is considered detected. If 32 or more time slots are selected for test-pattern
checking, this event could occur within one 125
μ
s frame. If only two time slots
are selected for test-pattern checking, then the test pattern will be detected after
16 frames.
Reserved.
Read as 0 or 1.
Error Detected.
This bit is set to 1 each time an error has been detected in the
test pattern once the test pattern has first been detected.
Reserved.
Read as 0.
BIST Complete.
When set to 1, this status bit indicates that the BIST sequence is
complete.
Bit Errors Inserted.
When set to 1, this status bit indicates that the request to
insert bit errors into the outgoing test pattern is complete.
5
TPD
4
3
—
ERD
2
1
—
BC
0
BEI
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TTSI1K16T | 1024-Channel, 16-Highway Time-Slot Interchanger(1024通道、16路干線時隙交換機) |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T | 2048-Channel, 32-Highway Time-Slot Interchanger(2048通道、32路干線時隙交換機) |
| TTSI4K32T | 4096-Channel, 32-Highway Time-Slot Interchanger |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TTSI1K16T3TL-DB | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| TTSI2K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI2K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:2048-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
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