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參數(shù)資料
| 型號： | TSPC860 |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Communication Processor |
| 中文描述： | 綜合通信處理器 |
| 文件頁數(shù)： | 81/93頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | TSPC860 |
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81
TSPC860 [Preliminary]
2129B–HIREL–12/04
Preparation For Delivery
Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
Certificate of Compliance
Atmel offers a certificate of compliances with each shipment of parts, affirming the prod-
ucts are in compliance either with MIL-STD-883 and guarantying the parameters not
tested at temperature extremes for the entire temperature range.
Power Consideration
The average chip-junction temperature, Tj, in
°
C can be obtained from the equation:
Tj = T
A
+ (P
D
·
Ο
JA
)
where
(1)
T
A
= Ambient temperature,
°
C
Ο
JA
= Package thermal resistance, junction to ambient,
°
C/W
P
D
= P
INT
+ P
I/O
P
INT
= I
DD
× V
DD
, watts – chip internal power
P
I/O
= Power dissipation on input and output pins – user determined
For most applications P
I/O
< 0.3 · P
INT
and can be neglected. If P
I/O
is neglected, an
approximate relationship between P
D
and T
J
is:
P
D
= K
÷
(T
J
+ 273
°
C)
Solving equations (1) and (2) for K gives:
K = P
D
· T (T
A
+ 273
°
C) +
Ο
JA
· P
D
where K is a constant pertaining to the particular part. K can be determined from equa-
tion (3) by measuring P
D
(at equilibrium) for a known T
A
. Using this value of K, the
values of P
D
and T
J
can be obtained by solving equations (1) and (2) iteratively for any
value of T
A
.
(2)
2
(3)
Layout Practices
Each V
DD
pin on the TSPC860 should be provided with a low-impedance path to the
board’s supply. Each GND pin should likewise be provided with a low-impedance path
to ground. The power supply pins drive distinct groups of logic on chip. The V
DD
power
supply should be bypassed to ground using at least four 0.1 μF bypass capacitors
located as close as possible to the four sides of the package. The capacitor leads and
associated printed circuit traces connecting to chip V
DD
and GND should be kept to less
than half an inch per capacitor lead. A four-layer board, employing two inner layers as
V
DD
and GND planes is recommended.
All output pins on the TSPC860 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflec-
tions caused by these fast output switching times. This recommendation particularly
applies to the address and data busses. Maximum PC trace lengths of six inches are
recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypass-
ing becomes especially critical in systems with higher capacitive loads because these
loads create higher transient current in the V
DD
and GND circuits. Pull up all unused
inputs or signals that will be inputs during reset. Special care should be taken to mini-
mize the noise levels on the PLL supply pins.
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