參數(shù)資料
型號(hào)： TSPC860
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁數(shù)： 49/93頁
文件大?。?/td> 1601K
代理商： TSPC860
49
TSPC860 [Preliminary]
2129B–HIREL–12/04
Figure 25.
Asynchronous External Master Memory Access Timing (GPCM Controlled – ACS = ’00’)
Figure 26.
Asynchronous External Master – Control Signals Negation Time
Notes:
1. The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level
sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLK-
OUT.
The timings I41, I42 and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no direct
relation with the total system interrupt latency that the TSPC860 is able to support.
CLKOUT
AS
A[0:31],
TSIZ[0:1],
R/W
CSx
B39
B40
B22
AS
B43
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
Table 8.
Interrupt Timing
Number
Characteristic
(1)
All Frequencies
Unit
Min
Max
I39
IRQx Valid to CLKOUT Rising Edge (Set Up Time)
6
–
ns
I40
IRQx Hold Time After CLKOUT
2
–
ns
I41
IRQx Pulse Width Low
3
–
ns
I42
IRQx Pulse Width High
3
–
ns
I43
IRQx Edge to Edge Time
4 × T
CLOCKOUT
–
–
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