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參數(shù)資料
| 型號： | TSPC860 |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Communication Processor |
| 中文描述： | 綜合通信處理器 |
| 文件頁數(shù)： | 3/93頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | TSPC860 |
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3
TSPC860 [Preliminary]
2129B–HIREL–12/04
Main Features
The Following is a List of the TSPC860’s Important Features:
Fully Static Design
Four Major Power Saving Modes
357-pin Ball Grid Array Packaging (Plastic)
32-bit Address and Data Busses
Flexible Memory Management
4-Kbyte Physical Address, Two-way, Set-associative Data Cache
4-Kbyte Physical Address, Two-way, Set-associative Instruction Cache
Eight-bank Memory Controller
–
Glueless Interface to SRAM, DRAM, EPROM, FLASH and Other Peripherals
–
Byte Write Enables and Selectable Parity Generation
–
32-bit Address Decodes with Bit Masks
System Integration Unit
–
Clock Synthesizer
–
Power Management
–
Reset Controller
–
PowerPC Decrementer And Time Base
–
Real-time Clock Register
–
Periodic Interrupt Timer
–
Hardware Bus Monitor and Software Watchdog Timer
–
IEEE 1149.1 JTAG Test Access Port
Communications Processor Module
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Embedded 32-bit RISC Controller Architecture for Flexible I/O
–
Interfaces to PowerPC Core Through On-chip Dual-port Ram And Virtual
DMA Channel Controller
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Continuous Mode Transmission And Reception On All Serial Channels
–
Serial DMA Channels For Reception And Transmission On All Serial
Channels
–
I/O registers with Open-drain Capability
–
Memory-memory and Memory-I/O Transfers with Virtual DMA Functionality
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