參數(shù)資料
型號(hào)： TSPC860
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁(yè)數(shù)： 33/93頁(yè)
文件大小： 1601K
代理商： TSPC860
33
TSPC860 [Preliminary]
2129B–HIREL–12/04
Table 7.
Bus Operation Timings
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B1
CLKOUT Period
30.30
30.30
25
30.30
20
30.30
15.15
30.30
ns
B1a
EXTCLK to CLKOUT Phase Skew
(EXTCLK > 15 MHz and MF
≤
2)
-0.90
0.90
-0.90
0.90
-0.90
0.90
-0.90
0.90
ns
B1b
EXTCLK to CLKOUT Phase Skew
(EXTCLK > 10 MHz and MF < 10)
-2.30
2.30
-2.30
2.30
-2.30
2.30
-2.30
2.30
ns
B1c
CLKOUT Phase Jitter (EXTCLK > 15 MHz and
MF
≤
2)
(1)
-0.60
0.60
-0.60
0.60
-0.60
0.60
-0.60
0.60
ns
B1d
CLKOUT Phase Jitter
-2
2
-2
2
-2
2
-2
2
ns
B1e
CLKOUT Frequency Jitter (MF < 10)
–
0.50
–
0.50
–
0.50
–
0.50
%
B1f
CLKOUT Frequency Jitter (10 < MF < 500)
–
2
–
2
–
2
–
2
%
B1g
CLKOUT Frequency Jitter (MF > 500)
–
3
–
3
–
3
–
3
%
B1h
Frequency Jitter on EXTCLK
(2)
–
0.50
–
0.50
–
0.50
–
0.50
%
B2
CLKOUT pulse width low
12.12
–
10
–
8
–
6.06
–
ns
B3
CLKOUT width high
12.12
–
10
–
8
–
6.06
–
ns
B4
CLKOUT rise time
(3)
–
4
–
4
–
4
–
4
ns
B5
CLKOUT fall time
(3)
–
4
–
4
–
4
–
4
ns
B7
CLKOUT to A(0:31), BADDR(28:30), RD/WR,
BURST, D(0:31), DP(0:3) Invalid
7.58
–
6.25
–
5
–
3.80
–
ns
B7a
CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3),
BDIP, PTR Invalid
7.58
–
6.25
–
5
–
3.80
–
ns
B7b
CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2),
IWP(0:2), LWP(0:1), STS
Invalid
(4)
7.58
–
6.25
–
5
–
3.80
–
ns
B8
CLKOUT to A(0:31), BADDR(28:30), RD/WR,
BURST, D(0:31), DP(0:3) valid
7.58
14.33
6.25
13
5
11.75
3.80
10.04
ns
B8a
CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3),
BDIP, PTR valid
7.58
14.33
6.25
13
5
11.75
3.80
10.04
ns
B8b
CLKOUT to BR, BG, VFLS(0:1), VF(0:2),
IWP(0:2), FRZ, LWP(0:1), STS valid
(4)
7.58
14.33
6.25
13
5
11.75
3.80
10.04
ns
B9
CLKOUT to A(0:31), BADDR(28:30), RD/WR,
BURST, D(0:31), DP(0:3), TSIZ(0:1), REG, RSV,
AT(0:3), PTR High Z
7.58
14.33
6.25
13
5
11.75
3.80
10.04
ns
B11
CLKOUT to TS, BB assertion
7.58
13.58
6.25
12.25
5
11
3.80
11.29
ns
B11a
CLKOUT to TA, BI assertion (when driven by the
Memory Controller or PCMCIA I/F)
2.50
9.25
2.50
9.25
2.50
9.25
2.50
9.75
ns
B12
CLKOUT to TS, BB negation
7.58
14.33
6.25
13
5
11.75
3.80
8.54
ns
B12a
CLKOUT to TA, BI negation (when driven by the
Memory Controller or PCMCIA interface)
2.50
11
2.50
11
2.50
11
2.50
9
ns
B13
CLKOUT to TS, BB High Z
7.58
21.58
6.25
20.25
5
19
3.80
14.04
ns
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