參數(shù)資料
型號(hào)： TSPC860
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁(yè)數(shù)： 18/93頁(yè)
文件大小： 1601K
代理商： TSPC860
18
TSPC860 [Preliminary]
2129B–HIREL–12/04
BADDR30
REG
Hi-Z
K4
Output
Burst Address 30—This output duplicates the value of A30 when the
following is true:
An internal master in the TSPC860 initiates a transaction on the
external bus
An asynchronous external master initiates a transaction
A synchronous external master initiates a single beat transaction
The memory controller uses BADDR30 to increment the address
lines that connect to memory devices when a synchronous external
master or an internal master initiates a burst transfer.
Register—When an internal master initiates an access to a slave
under control of the PCMCIA interface, this signal duplicates the
value of TSIZ0/REG. When an external master initiates an access,
REG is output by the PCMCIA interface (if it must handle the
transfer) to indicate the space in the PCMCIA card being accessed.
BADDR(28-
29)
Hi-Z
M3
M2
Output
Burst Address—Outputs that duplicate A(28-29) values when one of
the following occurs:
An internal master in the TSPC860 initiates a transaction on the
external bus
An asynchronous external master initiates a transaction
A synchronous external master initiates a single beat transaction
The memory controller uses these signals to increment the address
lines that connect to memory devices when a synchronous external
or internal master starts a burst transfer.
AS
Hi-Z
L3
Input
Address Strobe—Input driven by an external asynchronous master
to indicate a valid address on A(0-31). The TSPC860 memory
controller synchronizes AS and controls the memory device
addressed under its control.
PA[15]
RXD1
Hi-Z
C18
Bidirectional
General-Purpose I/O Port A Bit 15—Bit 15 of the general-purpose
I/O port A.
RXD1—Receive data input for SCC1.
PA[14]
TXD1
D17
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port A Bit 14—Bit 14 of the general-purpose
I/O port A.
TXD1—Transmit data output for SCC1. TXD1 has an open-drain
capability.
PA[13]
RXD2
E17
Bidirectional
General-Purpose I/O Port A Bit 13—Bit 13 of the general-purpose
I/O port A.
RXD2—Receive data input for SCC2.
PA[12]
TXD2
F17
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port A Bit 12—Bit 12 of the general-purpose
I/O port A.
TXD2—Transmit data output for SCC2. TXD2 has an open-drain
capability.
PA[11]
L1TXDB
G16
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port A Bit 11—Bit 11 of the general-purpose
I/O port A.
L1TXDB—Transmit data output for the serial interface TDM port B.
L1TXDB has an open-drain capability.
PA[10]
L1RXDB
J17
Bidirectional
General-Purpose I/O Port A Bit 10—Bit 10 of the general-purpose
I/O port A.
L1RXDB—Receive data input for the serial interface TDM port B.
Table 1.
Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
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