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參數(shù)資料
| 型號： | TSC2302IRGZRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | GREEN, PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 75/85頁 |
| 文件大?。?/td> | 1483K |
| 代理商： | TSC2302IRGZRG4 |
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TSC2302
SLAS394 – JULY 2003
Bits [15:4] — RESERVED
These bits are reserved, and should be written to 040h. If read, they read back as 040h.
Bits 3 — PLPN
Output PLL on the PENIRQ pin. This bit allows the user to receive the output of the audio codec internal PLL.
This bit is provided so the host processor can use the output of the PLL, to generate its I2S signals in sync with
an external MCLK or crystal oscillator. Writing a 1 to this bit connects the output of the PLL to the PENIRQ pin.
Otherwise, the PENIRQ pin operates as normal. The user must take care in using this function, as PENIRQ
signals are overridden.
Table 50. Output PLL on PENIRQ Pin
DEEMP
DESCRIPTION
0
PENIRQ operates as normal (default).
1
Output PLL on PENIRQ.
Bits 2 — COMK
Crystal Oscillator as MCLK. This bit allows the user to use the output of the internal crystal oscillator as the
MCLK for the audio codec. In this case, the MLCK pin must be grounded. In this case, the output of the crystal
oscillator replaces MCLK in all functions.
Table 51. Crystal Oscillator as MCLK
DEEMP
DESCRIPTION
0
Crystal oscillator and MCLK operates as normal (default).
1
Use crystal oscillator output as MCLK.
Bits [1:0] — RESERVED
These bits are reserved, and must be written to 0. If read, they read back as 0.
LAYOUT
The following layout suggestions provide optimum performance from the TSC2302. However, many portable
applications have conflicting requirements concerning power, cost, size, and weight. In general, most portable
devices have fairly clean power and grounds because most of the internal components are very low power. This
situation means less bypassing for the converter power and less concern regarding grounding. Still, each
situation is unique and the following suggestions should be reviewed carefully.
For optimum performance, care must be taken with the physical layout of the TSC2302 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and
digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single
conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily
affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output depends on the reference voltage, layout, and the
exact timing of the external event. The error can change if the external event changes in time with respect to the
internal conversion clock. The touch screen circuitry, as well as the audio headphone amplifiers, uses the
HPVDD/HPGND supplies for its power, and any noise on this supply may adversely affect performance in these
blocks.
As described earlier, the audio common-mode voltage VCM is derived directly through an internal resistor divider
between AVDD and AGND. Therefore, noise that couples onto AVDD/AGND is translated onto VCM and can
adversely impact audio performance. The reference pins for the audio data converters, VREF+/VREF-, should
also be kept as clean and noise-free as possible, since noise here affects audio DAC/ADC quality. De-coupling
capacitors are recommended between VREF+ and VREF-, in addition to a series resistance between VREF+
and the source of the voltage (such as connecting to the source providing AVDD).
77
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