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參數(shù)資料
| 型號： | TSC2302IRGZRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | GREEN, PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 58/85頁 |
| 文件大小： | 1483K |
| 代理商： | TSC2302IRGZRG4 |
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TSC2302
SLAS394 – JULY 2003
Table 23. Audio Data Input/Output Timing
Parameter
Symbol
Min
Max
BCKIN pulse cycle time
tBCY
300 ns
BCKIN pulse width high
tBCH
120 ns
BCKIN pulse width low
tBCL
120 ns
BCKIN rising edge to LRCIN edge
tBL
40 ns
LRCIN edge to BCKIN rising edge
tLB
40 ns
LRCIN pulse width
tLRP
tBCY ns
I2SDIN setup time
tDIS
40 ns
I2SDIN hold time
tDIH
40 ns
I2SDOUT delay time to BCKIN falling edge
tBDO
40 ns
I2SDOUT delay time to LRCIN edge
tLDO
40 ns
Rising time to all signals
tRISE
20 ns
Falling time to all signals
tFALL
20 ns
Audio Data Converters
The TSC2302 includes a stereo 20-bit audio DAC and a stereo 20-bit audio ADC. The DAC and ADC are both
capable of operating at 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz.
The DAC and ADC must operate at the same sampling rate.
When the ADC or DAC is operating, the part requires an audio MCLK input, which should be synchronous to the
I2S bus clock. The MCLK can be 256/384/512 times the I2S LRCLK rate. An internal PLL takes any of these
possible input clocks and generates a digital clock for use by the internal circuitry of either 44.1 kHz x 512 =
22.5792 MHz (when 44.1 kHz submultiple sample-rates are selected) or 48 kHz x 512 = 24.576 MHz (when 48
kHz submultiple sample-rates are selected). The user is required to set the MCLK bits (Bits[7:6], Reg 00h, Pg 2)
to tell the part the ratio between MCLK and the I2S LRCLK rate (there is no specific phase alignment requirement
between MCLK and BCLK). The user is also required to set the I2SFS bits (Bits[5:2], Reg 00h, Pg 2) to tell the
part what sample rate is in use. When the user is using either 44.1 kHz or 48-kHz sampling rates, and providing
a 512 x Fs MCLK, the internal PLL is powered down, as MCLK can be used directly to clock the internal circuitry.
This reduces power consumption.
If the user wishes to change sampling rates, the data converters (both DACs and ADCs) must be muted, then
powered down. The LRCLK and BCLK rates must then be changed. Next the user must write the appropriate
settings to the MCLK, I2SFS, and I2SFM bits, then power up the data converters. Finally, the data converters
can be unmuted.
Due to the wide supply range over which this part must operate, the audio does not operate on an internal
reference voltage. The common-mode voltage that the single-ended audio signals are referenced to is set by a
divider between the analog supplies and is given by 0.4 x AVDD. The reference voltages used by the audio
codec must be provided as inputs to the part at the Vref+/Vref- pins and are intended to be connected to the
same voltage levels as AVDD and AGND, respectively. Because of this arrangement, the voltages applied to
AVDD, AGND, Vref+, and Vref- should be kept as clean and noise-free as possible.
DAC Digital Volume Control
The DAC digital effects processing block implements a digital volume control that can be set through the SPI
registers. The volume level can be varied from 0 dB to -63.5 dB in 0.5-dB steps independently for each channel.
The user can mute each channel independently by setting the mute bits in the DAC volume control register (Reg
02h, Pg 2). There is a soft-stepping algorithm included in this block, which only changes the actual volume every
20 s, either up or down, until the desired volume is reached. This speed of soft-stepping can be slowed to once
every 40 s through the SSRTE bit (Bit 1, Reg 04h, Pg 2).
61
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