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參數資料
| 型號： | TSC2302IRGZRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | GREEN, PLASTIC, VQFN-48 |
| 文件頁數： | 60/85頁 |
| 文件大?。?/td> | 1483K |
| 代理商： | TSC2302IRGZRG4 |
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N0 ) 2 N1 Z–1 ) N2 Z–2
32768–2 D1 Z–1–D2 Z–2
N3 ) 2 N4 Z–1 ) N5 Z–2
32768–2 D4 Z–1–D5 Z–2
(13)
Default Bass-Boost Transfer Function 48 kHz Mode
1
10
100
1000
10000
100000
Frequency (Hz)
0
–0.5
–1
–1.5
–2
–2.5
–3
–3.5
Gain
(dB)
TSC2302
SLAS394 – JULY 2003
DAC Programmable Digital Effects Filter
The DAC digital effects processing block also includes a fourth order digital IIR filter with programmable
coefficients (independently programmable per channel). The filter transfer function is given by:
The N and D coefficients are set via SPI registers, and this filter can be enabled or disabled via the BASS bit (Bit
1, Reg 05h, Pg 2). This functionality can implement a number of different functions, such as bass-boost (default),
treble-boost, mid-boost, or other equalization. This transfer function(s) can be determined by the user and loaded
to the TSC2302 at power-up, and the feature can then be switched on or off by the user during normal operation.
If a filter with gain over 0 dB is designed and used, and large-scale signals are played at high amplitude through
the DAC, overloading and undesirable effects can occur.
The default coefficients at reset are given by:
N0 = N3 = 27618
D1 = D4 = 32130
N1 = N4 = -27033
D2 = D5 = -31505
N2 = N5 = 26461
which implements the bass-boost transfer function shown in Figure 71, having a 3-dB attenuation for signals
above approximately 150 Hz when operating at a 48-kHz sampling rate. All coefficients are represented by 16-bit
twos complement integers with values ranging from -32768 to +32767.
Figure 71. Transfer Function of Default Bass-Boost Filter Coefficients at 48-kHz Sampling Rate
Audio ADC
The audio ADC consists of a 4th order multi-bit analog delta-sigma modulator, followed by a digital decimation
filter. The digital output data is then passed to the bus interface for transmission back to the CPU.
The analog modulator is a fully differential switched-capacitor design with multi-bit quantizer and dynamic
element matching to avoid mismatch errors. The modulator operates at an oversampling ratio of 128 for all
sample rates. The input to the ADC is filtered by a single-pole analog filter with -3-dB point at approximately 500
kHz for antialiasing. This analog filter uses a single off-chip 1 nF cap per ADC (at the AFILT pins) and on-chip
resistor.
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