- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98303 > TSC2302IRGZRG4 (TEXAS INSTRUMENTS INC) SPECIALTY CONSUMER CIRCUIT, PQCC48 PDF資料下載
參數(shù)資料
| 型號(hào)： | TSC2302IRGZRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | GREEN, PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 24/85頁 |
| 文件大?。?/td> | 1483K |
| 代理商： | TSC2302IRGZRG4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
www.ti.com
TSC2302
SLAS394 – JULY 2003
Secondary Configuration Register (Page 1, Address 06H):
This register allows the user to read the status of the DAV pin through the SPI interface. It also controls the audio
codec PLL.
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MSB
LSB
SDAV
RESV
PLLO
PCTE
PDC3
PDC2
PDC1
PDC0
A3
A2
A1
A0
N3
N2
N1
N0
Bit 15 — SDAV (read only)
SPI Data Available. This read-only bit mirrors the function of the DAV pin. This bit is provided so that the host
processor can poll the SPI interface to see whether data is available, without dedicating a GPIO pin from the host
processor to the TSC2302 DAV pin. This bit is normally high, goes low when touch screen or keypad data is
available, and is reset high when all the new data has been read. When written to, this bit becomes KBC1,
operation detailed below.
Table 19. SPI Data Available (Read Only)
SDAV
DESCRIPTION
0
Touchscreen data is available.
1
No new data available (default)
Bit 13 — PLLO
PLL Output on GPIO_0. This bit allows the user to receive the output of the audio codec internal PLL. This bit is
provided so the host processor can use the output of the PLL, to generate its I2S signals in sync with an external
MCLK or crystal oscillator. Writing a 0 to this bit connects the output of the PLL to the GPIO_0 pin. Otherwise,
the GPIO_0 pin operates as normal.
Table 20. PLL Output
PLLO
DESCRIPTION
0
Output PLL on GPIO_0.
1
GPIO_0 operates as normal (default).
Bit 12 — PCTE
PLL Control Enable. This bit allows the user to manually control the audio codec internal PLL. This allows the
user to modify the contents of bits [11-0] to control the audio codec PLL. Writing a 0 to this bit enables manual
control of the PLL. Otherwise, the PLL is set automatically based on the settings of MCLK [1:0] and I2SFS[3:0] in
the audio control register (bits 7-2 in register 00h, page 2).
Table 21. PLL Control Enable
PLLO
DESCRIPTION
0
Allows modification of bits [11:0].
1
PLL operates as normal, no manual override (default).
30
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSDC4872IJT | 1 W, 1 CHANNEL, AUDIO AMPLIFIER, PBGA8 |
| TS4872IJT | 1 W, 1 CHANNEL, AUDIO AMPLIFIER, PBGA8 |
| TSH103ID | 3 CHANNEL, VIDEO AMPLIFIER, PDSO8 |
| TSH103IDT | 3 CHANNEL, VIDEO AMPLIFIER, PDSO8 |
| TSH120ICT | SPECIALTY CONSUMER CIRCUIT, PDSO6 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSC2303IZQZ | 制造商:Texas Instruments 功能描述: |
| TSC2303IZQZR | 制造商:Texas Instruments 功能描述: |
| TSC236 | 制造商:TSC 制造商全稱:Taiwan Semiconductor Company, Ltd 功能描述:High Voltage NPN Transistor |
| TSC236CIC0 | 制造商:TSC 制造商全稱:Taiwan Semiconductor Company, Ltd 功能描述:High Voltage NPN Transistor |
| TSC236CZ C0 | 功能描述:兩極晶體管 - BJT High voltage NPN Transistor RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發(fā)射極最大電壓 VCEO:- 40 V 發(fā)射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產(chǎn)品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。