- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄385949 > TSB42AA4I (Texas Instruments, Inc.) IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | TSB42AA4I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| 中文描述： | 1394消費(fèi)電子產(chǎn)品鏈路層控制器 |
| 文件頁(yè)數(shù)： | 53/183頁(yè) |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AA4I |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)當(dāng)前第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)
41
4 Internal Functions
4.1
Data Buffers
4.1.1
Byte Stacking and Endianness
All access to and from the internal transmit and receive FIFOs is 32 bits wide. Since the HSDI is only 8 bits
(or one byte) wide, a byte stack/unstack operation must be performed at the HSDI data port. The order in
which bytes are stacked/unstacked determines the endianness. This
endianness
is programmable. (note
that the endianess setting does not affect the stacking of individual bits into the first byte buffer for the serial
mode. This stacking is fixed and always expects to receive the bits in order
Selecting big endian would put the first byte received into the most significant bit location of the stacking
buffer, and each consecutive byte into successively lower significant byte locations. Selecting little endian
would put the first byte received into the least significant byte location and each consecutive byte into
successively higher significant byte locations.
The endianess of the byte stacking operation can be programmed to either
little endian
or
big endian
(default) independently for each port.
4.1.2
Buffer Overflow/Underflow Status
The
GPIO
signals can be used for applications where the HSDI host needs to burst data into a ceLynx
transmit buffer and will need a look ahead indicator of the buffer’s content status. This allows for a more
efficient memory transfer from the applications memory space to the transmit FIFO since the host controller
could start and stop memory transfers on appropriate boundaries. The full and empty levels of each buffer
are programmable via CFRs by the host controller to allow the user customization when the controller is
notified of a pending full or empty status. Since these signals are application dependent, they are routed
to multifunction pins (
GPIO
) on the device. The buffers also have programmable watermarks, which can
cause interrupts to the external CPU.
4.1.3
Data Buffer Setup
The data buffer can be programmed in up to eight different partitions. Because of this, the registers are
usually described once, but have eight different instances to control the eight different buffers. For example,
the DB(N)CFG0 register is the description for HSDI buffer settings. The actual settings for buffer 0 are
programmed in register 0x15C. The settings for buffer 1 are programmed in register 0x174.
The data buffers have default settings for data type and direction. The transmit data path has default values
for header registers which match the buffer defaults.
If the buffer defaults are changed, the header registers must be reprogrammed to reflect the change.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB42AA4PDT | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AA4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AA9I | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| TSB42AA9IPZT | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| TSB42AB4I | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB42AA4IPDT | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AA4PDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AA4PDTG4 | 功能描述:1394 接口集成電路 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AA4PDTR | 制造商:Texas Instruments 功能描述: |
| TSB42AA4PGE | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。