![](http://datasheet.mmic.net.cn/390000/TSB42AA4I_datasheet_16839080/TSB42AA4I_170.png)
673
0x348 RXDPINT Receive Data Path Interrupts
BIT
NAME
TYPE
RESET
FUNCTION
31:24
PKTRCVERR(N)
RCU
0
Packet receive error There is an indication for each of the eight
buffers which is set to 1 whenever a 1394 packet is aborted.
23:16
PKTRCVD(N)
RCU
0
Packet received – There is an indication for each of the eight buffers
which is set to 1 whenever a 1394 packet is confirmed into the
corresponding buffer.
15
EVODCHNGB
RCU
0
Even/odd bit change stream B Set to 1 when the even/odd bit for
stream B changes.
14
EVODCHNGA
RCU
0
Even/odd bit change stream A Set to 1 when the even/odd bit for
stream A changes.
13
EMIERRB
RCU
0
Encryption mode indicator error stream B When the detected EMI
setting is different from the EMI setting in the cipher, this bit is set to 1 to
indicate an EMI error.
12
EMIERRA
RCU
0
Encryption mode indicator error stream A When the detected EMI
setting is different from the EMI setting in the cipher, this bit is set to 1 to
indicate an EMI error.
11
DVSPLITERRB
RCU
0
Digital video split error stream B Set to 1 when an error occurs when
receiving DV headers for DV stream B into a separate buffer.
10
DVSPLITERRA
RCU
0
Digital video split error stream A Set to 1 when an error occurs when
receiving DV headers for DV stream A into a separate buffer.
9
DVSEQERRB
RCU
0
Digital video sequence error stream B Set to 1 when a sequence
error is detected in stream B.
8
DVSEQERRA
RCU
0
Digital video sequence error stream A Set to 1 when a sequence
error is detected in stream A.
7
RSVD
RW
0
Reserved – A write to this location has no effect. A read returns 0.
6
SNTRJCT
RCU
0
Sent reject Set to 1 when a received packet has been acknowledged
with the ACK_BUSY_X.
5
DATACRCERR
RCU
0
Data CRC error This bit is set to 1 by hardware when the data CRC
check failed for a receive packet.
4
BUFADDRERR
RCU
0
Buffer address error – Set to 1 when a packet has been received but no
valid buffer address could be generated. The packet was aborted.
3
PKTTYPERR
RCU
0
Packet type error – Set to 1 when a 1394 packet with an illegal tCode is
received and aborted.
2
BSYREQ
RCU
0
Busy requested – This bit is set to 1 by hardware to indicate that a
receive packet was busied off because the receive state machines
were not idle when the start of reception was detected.
1
CMDRSTRCVD
RCU
0
Command reset received When CMDRSTRCVD is set to 1, the link
has received a 1394 quadlet write request to the Reset_Start CSR
register (target address is FFFF_F000_000Ch)
0
SIDEND
RCU
0
Self-ID end Set to 1 when the self-ID phase is over and all self-ID
packets have been confirmed into the FIFO.