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參數(shù)資料
| 型號(hào)： | TSB42AA4I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| 中文描述： | 1394消費(fèi)電子產(chǎn)品鏈路層控制器 |
| 文件頁數(shù)： | 26/183頁 |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AA4I |
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31
3 External Interfaces
The ceLynx has four external interfaces; the high-speed data interface (HSDI), the microcontroller interface
(MCIF), the physical-layer interface, and a two-wire serial interface for an external EEPROM. The HSDI and
MCIF each support multiple modes designed for maximum flexibility and ease of use. The physical layer
interface conforms to the IEEE 1394-1995 and 1394.a standards and allows the ceLynx to operate
seamlessly with industry standard 100-, 200-, and 400-Mbps physical-layer devices. This includes the
Texas Instruments family of 400 Mbps PHYS (TSB41LV0X). The two-wire serial interface gives a connection
to EEPROM for easy loading of CFR and CSR information
This section includes the interface, functional operation, and detailed timing information for all modes of
each interface.
3.1
Microcontroller Interface (MCIF)
The ceLynx has a host controller interface that is designed to interface seamlessly with 68000/68020 style
processors. This interface is completely asynchronous. The interface consists of 16 data lines, 9 address
lines, and various control signals. All signals are resynchronized internally to a 50-MHz clock derived from
the SCLK input from the physical layer device. The host controller interface operates seamlessly with
various vendors’ MPEG2 transport chipsets for ease of use.
Both 32-bit and 16-bit transactions are supported on the microcontroller interface. When using 32-bit
accesses the host supplies only one address, then follows with two data phases. The link microcontroller
interface automatically increments the address for the second data phase. For 16-bit access, each
transaction requires a separate address. Each 16-bit access is independent of any other transaction. The
microcontroller interface uses the MCIF_S32 signal to determine if the current access is 32- or 16-bit. The
MCIF_S32 signal state should not change in the middle of an access. It can change in between accesses.
The 16-bit transaction capability allows the host more efficient access since it eliminates the need for the
host to disable interrupts between upper and lower doublet accesses. Disabling interrupts is required if only
full quadlet (32-bit) access is supported for every CFR access.
For a 32-bit read, the upper and lower doublets are time independent. When the first doublet is accessed,
a snapshot of the entire 32-bit register is captured. The second doublet access uses the snapshot value.
The snapshot is not used for 16-bit register access. Each 16-bit access results in the most up-to-date
doublet value.
Note that nonquadlet aligned addressing is not supported. The host controller can only access the upper
half or lower half of any 32-bit CFR. For example, the version ID CFR is located at addresses 0x000 and
0x002. The host is not allowed to perform a 32-bit access starting at address 003h. This would, in effect,
be an attempt to write to addresses 003h and 004h. The 004h is located within a separate CFR. However,
using 16-bit transactions, the user can access either upper or lower half of all 32-bit CFRs independently.
NOTE:
The host interface does not support time stamping or encryption.
For reads of time-sensitive registers (such as CYCLE TIMER), use 32-bit reads
if high accuracy is required. For a 32-bit read, the register value is copied and is
used for both the upper and lower 16-bit reads.
During a 16-bit read operation, the current doublet being addressed returns the
current data value. This may present problems for time-sensitive registers, such
as the CYCLE TIMER. The first 16-bit read returns the upper 16 bits. The second
16-bit read returns the lower 16 bits, but the amount of time between the first and
second reads results in a difference between the upper and lower cycle timer
values.
When ceLynx is programmed to use 32-bit host access, only big endian mode is
supported for all data access through the host.
Status of the MCIF_STRB pin. MCIF_ACK function depends on MCIF_STRB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB42AA4PDT | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AA4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AA9I | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| TSB42AA9IPZT | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| TSB42AB4I | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB42AA4IPDT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AA4PDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AA4PDTG4 | 功能描述:1394 接口集成電路 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AA4PDTR | 制造商:Texas Instruments 功能描述: |
| TSB42AA4PGE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
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