參數(shù)資料
型號(hào)： TPS65800RTQTG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 電源管理
英文描述： 8-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC56
封裝： 8 X 8 MM, GREEN, PLASTIC, QFN-56
文件頁(yè)數(shù)： 22/98頁(yè)
文件大?。?/td> 2077K
代理商： TPS65800RTQTG4
www.ti.com
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
BIT0
LSB
ACKNOWLEDGE
(hA orbqA
)
STOP
CONDITION
(P)
SCL
SDA
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
BIT 0
LSB
NOT
ACKNOWLEDGE
(hNorbqN)
STOP
CONDITION
(P)
SCL
SDA
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB
BIT 6
SCL
SDA
DATA LINE
STABLE
DATA
CHANGE
ALLOWED
BIT 5-1
I2C Read and Write Operations
SLVS606C – SEPTEMBER 2005 – REVISED FEBRUARY 2007
Table 2. I2C Naming Conventions Used
CONDITION
CODE
START sent from host
S
STOP sent from host
P
TPS65800 I2C slave address sent from host, bus direction set from host to TPS65800 (WRITE)
hA0
TPS65800 register address sent from TPS65800, bus direction is from TPS65800 to host (READ)
hA1
Non-valid I2C slave address sent from host
hA_N
Valid TPS65800 register address sent from host
HCMD
Non-valid TPS65800 register address sent from host
HCMD_N
I/O data byte (8 bits) sent from host to TPS65800
hDATA
I/O data byte (8 bits) sent from TPS65800 to host
bqDATA
Acknowledge (ACK) from host
hA
Not acknowledge (NACK) from host
hN
Acknowledge (ACK) from TPS65800
bqA
Not acknowledge (NACK) from TPS65800
bqN
Figure 24. I2C operation waveforms
For normal data transfers, SDA is allowed to change only when SCL is low, and one clock pulse is used per bit
of data. The SDA line must remain stable whenever the SCL line is high, as SDA changes when SCL is high are
reserved for indicating the start and stop conditions. Each data transfer is initiated with a start condition and
terminated with a stop condition.
When addressed, the TPS65800 device generates an acknowledge bit after the reception of each byte by
pulling the SDA line Low. The master device (microprocessor) must generate an extra clock pulse that is
associated with the acknowledge bit. After the acknowledge/not acknowledge bit the TPS65800 leaves the data
line high, enabling a STOP condition generation.
The TPS65800 supports the standard I2C one byte Write. The basic I2C read protocol has the following steps:
Host sends a start and sets TPS65800 I2C slave address in write mode.
TPS65800 ACKs that this is a valid I2C address and that the bus is configured for write.
Host sends TPS65800 register address.
TPS65800 ACKs that this is a valid register and stores the register address to be read.
Host sends a repeated start and TPS65800 I2C slave address, reconfiguring the bus for read.
TPS65800 ACKs that this is a valid address and that bus is reconfigured.
Bus is in read mode, TPS65800 starts sending data from selected register.
29
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