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參數(shù)資料
| 型號： | TPS65800RTQTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 8-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC56 |
| 封裝： | 8 X 8 MM, GREEN, PLASTIC, QFN-56 |
| 文件頁數(shù)： | 21/98頁 |
| 文件大?。?/td> | 2077K |
| 代理商： | TPS65800RTQTG4 |
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SERIAL INTERFACE
Overview
Register Default Values
I2C Address
Incremental Read
I2C Bus Release
Sleep Mode Operation
I2C Bus Error Recovery
I2C Communication Protocol
SLVS606C – SEPTEMBER 2005 – REVISED FEBRUARY 2007
The TPS65800 is compatible with a host-controlled environment, with internal parameters and status information
accessible via an I2C interface. An I2C communication port provides a simple way for an I2C compatible host to
access system status information and reset fault modes, functioning as a SLAVE port enabling I2C compatible
hosts to WRITE to or to READ from internal registers. The TPS65800 I2C port is a 2-wire bidirectional interface
using SCL (clock) and SDA (data) pins; the SDA pin is open drain and requires an external pullup. The I2C is
designed to operate at SCL frequencies up to 400 kHz. The standard 8 bit command is supported, the CMD part
of the sequence is the 8 bit register address to READ from or to WRITE to.
The internal TPS65800 registers are loaded during the initial power-up from an internal, non-volatile memory
bank. The power-up default values are described in the sections detailing the registers functionality.
The register contents remain intact as long as OUT pin voltage remains above the internal UVLO threshold,
VUVLO When the OUT pin voltage falls below the VUVLO threshold all register bits are reset to the internal power
up default.
The I2C specification contains several global addresses, which the slaves on the bus are required to respond to.
The TPS65800 only responds (ACK) to addresses 0x90 and 0x91 and does not respond (NACK) to any other
address.
Table 1. TPS65800 I2C Read/Write Address
BYTE
BIT
MSB
6
5
4
3
2
1
LSB
TPS65800 I2C WRITE ADDRESS
1
0
1
0
TPS65800 I2C READ ADDRESS
1
0
1
0
1
I/O DATA BUS
B7
B6
B5
B4
B3
B2
B1
B0
The TPS65800 does not support incremental read operations. Each register must be accessed in a single read
operation.
The TPS65800 I2C engine does not create START or STOP states on the I2C bus during normal operation.
When the sleep mode is set SDAT is held LO by the TPS65800. The overall system operation is not affected, as
in sleep mode all TPS65800 integrated supplies are disabled and no power is available for any external devices
connected to the TPS65800 SDAT pin. When sleep mode ends the SDAT pin is released before the TPS65800
integrated regulated supplies are enabled. See section on System Sequencing and TPS65800 Operating Modes
for additional details on sleep mode operation.
The I2C bus specification does not define a method to be used when recovering from a host side bus error.
During a read operation, the SDA pin can be left in a LO state if the host has not sent enough SCL pulses to
complete a transaction (i.e., host side bus error). The TPS65800 clears any SDA LO condition if 10 SCL pulses
are sent by the host, enabling recovery from host side bus error events.
The following conventions are used when describing the communication protocol:
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