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4.1 System Interconnect Block Diagram
SCR5
SCR1
Bridge2
CF/ATA
VLYNQ
EMAC
USB 2.0
SCR2
Bridge1
Bridge7
ARM
C64x+
C
M
L2 Cache
VICP
Bridge6
Bridge5
SCR3
VPSS
EDMA3TC1
Bridge3
ARM
TCM
C64x+
L2/L1
S
DDR2 Ctrl
(Mem/Reg)
SCR6
CF/ATA Reg
USB Reg
EMAC Reg
EMAC Ctrl Mod Reg
EMAC Ctrl Mod RAM
MDIO
VPSS Reg
SPI 0/1
GPIO
AINTC
System Reg
PSC
PLLC 0
PLLC 1
Bridge9
Bridge8
SCR7
ASP
VLYNQ
MMC/SD
EMIFA/NAND
SCR8
UART0
UART1
UART2
I2C
PWM0
PWM1
PWM2
Timer 0
Timer 1
Timer 2
SCR4
EDMA3CC
EDMA3TC0
EDMA3TC1
32
32
32
32
64
32
32
32
32
64
64
64
64
64
Read
Write
Read
Write
64
64
64
64
64
128
256
32
32
32
32
32
32
64
64
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
DSP/2 Clock Rate
DSP/3 Clock Rate
DSP/6 Clock Rate
EDMA3TC0
MXI/CLKIN Rate
32
32
HPI
32
HPI
32
TMS320DM6443
Digital Media System-on-Chip
SPRS282E–DECEMBER 2005–REVISED MARCH 2007
Figure 4-1
displays the DM6443 system interconnect block diagram. The following is a list that helps
interpret this diagram:
The direction of the arrows indicates either bus master or bus slave.
The arrow originates at a bus master and terminates at a bus slave.
The direction of the arrows does not indicate the direction of data flow. Data flow is typically
bi-directional for each of the documented bus paths.
The pattern of each arrow's line indicates the clock rate at which it is operating, either DSP/2, DSP/3,
or DSP/6 clock rate.
Some peripherals may have multiple instances shown in the diagram. A peripheral may have multiple
instances shown for a variety of reasons, some of which are described below:
–
The peripheral/module has master port(s) for data transfers, as well as slave port(s) for register
access, data access, and/or memory access. Examples of these peripherals are C64x+
megamodule, EDMA3, CF/ATA, USB, EMAC, VPSS, VLYNQ, and HPI.
–
The peripheral/module has a master port as well as slave memories. Examples of these are the
C64x+ megamodule and the ARM subsystem.
Figure 4-1. System Interconnect Block Diagram
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