參數(shù)資料
型號： TMS320VC5409PGE-100
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 7/78頁
文件大?。?/td> 1018K
代理商： TMS320VC5409PGE-100
TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
NAME
DESCRIPTION
I/O
INTERNAL
PIN STATE
TERMINAL
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)
NMI
Schmitt
trigger
I
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or
the IMR. When NMI is activated, the processor traps to the appropriate vector location.
RS
Schmitt
trigger
I
Reset. RS causes the DSP to terminate execution and causes a reinitialization of the CPU and
peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program
memory. RS affects various registers and status bits.
MP/MC
I
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is
selected, and the internal program ROM is mapped into the upper program memory space. If the
pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed
from program space. MP/MC is only sampled at reset, and the MP/MC bit of the PMST register can
override the mode that is selected at reset.
MULTIPROCESSING SIGNALS
BIO
Schmitt
trigger
I
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor
executes the conditional instruction. For the XC instruction, the BIO condition is sampled during
the decode phase of the pipeline; all other instructions sample BIO during the read phase of the
pipeline.
XF
O/Z
External flag output (latched software-programmable signal). XF is set high by the SSBX XF
instruction, set low by the RSBX XF instruction or by loading ST1. XF is used for signaling other
processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into
the high-impedance state when OFF is low, and is set high at reset.
MEMORY CONTROL SIGNALS
DS
PS
IS
O/Z
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
accessing a particular external memory space. Active period corresponds to valid address
information. DS, PS, and IS are placed into the high-impedance state in the hold mode; the signals
also go into the high-impedance state when OFF is low.
MSTRB
O/Z
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus
access to data or program memory. MSTRB is placed in the high-impedance state in the hold mode;
it also goes into the high-impedance state when OFF is low.
READY
I
Data ready. READY indicates that an external device is prepared for a bus transaction to be
completed. If the device is not ready (READY is low), the processor waits one cycle and checks
READY again. Note that the processor performs ready detection if at least two software wait states
are programmed. The READY signal is not sampled until the completion of the software wait states.
R/W
O/Z
Read/write signal. R/W indicates transfer direction during communication to an external device.
R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write
operation. R/W is placed in the high-impedance state in hold mode; it also goes into the
high-impedance state when OFF is low.
IOSTRB
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus
access to an I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also
goes into the high-impedance state when OFF is low.
HOLD
I
Hold. HOLD is asserted to request control of the address, data, and control lines. When
acknowledged by the ’C54x, these lines go into the high-impedance state.
HOLDA
O/Z
Hold acknowledge. HOLDA indicates that the ’5409 is in a hold state and that the address, data,
and control lines are in the high-impedance state, allowing the external memory interface to be
accessed by other devices. HOLDA also goes into the high-impedance state when OFF is low.
MSC
O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more
software wait states are enabled, the MSC pin goes low during the last of these wait states. If
connected to the READY input, MSC forces one external wait state after the last internal wait state
is completed. MSC also goes into the high-impedance state when OFF is low.
IAQ
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on
the address bus. IAQ goes into the high-impedance state when OFF is low.
I = Input, O = Output, Z = High-impedance, S = Supply
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320VC5409PGE100 制造商:Texas Instruments 功能描述:Digital Signal Processor IC
TMS320VC5409PGE-80 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
TMS320VC5409ZGU100 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
TMS320VC5409ZGU-80 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
TMS320VC5410AGGU1 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
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