參數資料
型號: TMS320VC5409PGE-100
元件分類: 數字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數字信號處理器
文件頁數: 24/78頁
文件大?。?/td> 1018K
代理商: TMS320VC5409PGE-100
TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock generator (continued)
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the ’5409
device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of
the ’5409 to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in
software-programmable PLL can be configured in one of two clock modes:
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved
using the PLL circuitry.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be
completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon
reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the
CLKMD1 – CLKMD3 pins as shown in Table 9.
Table 9. Clock Mode Settings at Reset
CLKMD1
CLKMD2
CLKMD3
CLKMD
RESET VALUE
E007h
CLOCK MODE
0
0
0
PLL x 15
0
0
1
9007h
PLL x 10
0
1
0
4007h
PLL x 5
1
0
0
1007h
PLL x 2
1
1
0
F007h
PLL x 1
1
1
1
0000h
1/2 (PLL disabled)
1
0
1
F000h
1/4 (PLL disabled)
0
1
1
Reserved
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相關代理商/技術參數
參數描述
TMS320VC5409PGE100 制造商:Texas Instruments 功能描述:Digital Signal Processor IC
TMS320VC5409PGE-80 功能描述:數字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
TMS320VC5409ZGU100 功能描述:數字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
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