參數(shù)資料
型號(hào): TMS320VC5409PGE-100
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 23/78頁(yè)
文件大小: 1018K
代理商: TMS320VC5409PGE-100
TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
23
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multichannel buffered serial ports (McBSPs) (continued)
Table 8. Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions
BIT
NAME
FUNCTION
15
GSYNC
Sample rate generator clock synchronization. Only used when the external clock (CLKS) drives the sample rate
generator clock (CLKSM=0)
GSYNC = 0
GSYNC = 1
The sample rate generator clock (CLKG) is free-running.
The sample rate generator clock (CLKG) is running. But CLKG is resynchronized and frame sync
signal (FSG) is generated only after detecting the receive frame synchronization signal (FSR). Also,
frame period (FPER) is a don’t care because the period is dictated by the external frame sync pulse.
14
CLKSP
CLKS polarity clock edge select. Only used when the external clock (CLKS) drives the sample rate generator clock
(CLKSM=0).
CLKSP = 0
CLKSP = 1
Rising edge of CLKS generates CLKG and FSG.
Falling edge of CLKS generates CLKG and FSG.
13
CLKSM
McBSP sample rate generator clock mode
SCLKME = 0
(in PCR)
CLKSM = 0
CLKSM = 1
Sample rate generator clock derived from the CLKS pin
Sample rate generator clock derived from CPU clock
SCLKME = 1
(in PCR)
CLKSM = 0
CLKSM = 1
Sample rate generator clock derived from CLKR pin
Sample rate generator clock derived from CLKX pin
12
FSGM
Sample rate generator transmit frame synchronization mode. Used when FSXM=1 in the PCR.
FSGM = 0
FSGN = 1
Transmit frame sync signal (FSX) due to DXR(1/2) copy
Transmit frame sync signal driven by the sample rate generator frame sync signal (FSG)
11 – 0
FPER
Frame period. This determines when the next frame sycn signal should become active. Range: up to 212;
1 to 4096 CLKG periods.
hardware timer
The ’5409 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer is
decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is
generated. The timer can be stopped, restarted, reset, or disabled by specific control bits.
clock generator
The clock generator provides clocks to the ’5409 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock
input is then divided by two (DIV mode) to generate clocks for the ’5409 device, or the PLL circuit can be used
(PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing
use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that, once
synchronized, locks onto and tracks an input clock signal.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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