
TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Table of Contents
Internal Oscillator with External Crystal
Divide-by-Two/Divide-by-Four Clock Option
Multiply-by-N Clock Option
Memory and Parallel I/O Interface Timing
Timing For Externally Generated Wait States
HOLD and HOLDA Timings
Reset, BIO, Interrupt, and MP/MC Timings
Instruction Acquisition (IAQ), Interrupt
Acknowledge (IACK), External Flag (XF),
and TOUT Timings
Multichannel Buffered Serial Port Timing
HPI8 Timing
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HPI16 Timing
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Mechanical Data
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40
41
42
43
49
53
55
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57
59
67
72
76
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Description
Pin Assignments
Terminal Functions
Memory
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On-chip Peripherals
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Memory-mapped Registers
McBSP Control Registers And Subaddresses
DMA Subbank Addressed Registers
Interrupts
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Documentation Support
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Absolute Maximum Ratings
Recommended Operating Conditions
Electrical Characteristics
Parameter Measurement Information
2
5
6
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11
15
30
33
33
35
37
38
38
39
39
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description
The TMS320VC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5409 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis
of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the
high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition,
data can be transferred between data and program spaces. Such parallelism supports a powerful set of
arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition,
the ’5409 includes the control mechanisms to manage interrupts, repeated operations, and function calls.