參數(shù)資料
型號(hào): TMS320VC5409PGE-100
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 38/78頁(yè)
文件大?。?/td> 1018K
代理商: TMS320VC5409PGE-100
TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
absolute maximum ratings over specified temperature range (unless otherwise noted)
Supply voltage I/O range, DV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage core range, CV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, T
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS.
–0.3 V to 4.0 V
–0.3 V to 2.4 V
–0.3 V to 4.5 V
–0.3 V to 4.5 V
–40
°
C to 100
°
C
–55
°
C to 150
°
C
recommended operating conditions
MIN
NOM
MAX
UNIT
DVDD
CVDD
Device supply voltage, I/O§
Device supply voltage, core§
3
3.3
3.6
V
1.71
1.8
1.98
V
VSS
Supply voltage, GND
0
V
VIH
High level input voltage I/O
High-level input voltage, I/O
RS, INTn, NMI, BIO, BCLKR0, BCLKR1,
BCLKR2, BCLKX0, BCLKX1, BCLKX2, HAS,
HCS, HDS1, HDS2, TCK, CLKMDn, DVDD =
3.3
0.3 V
TRST
2.2
DVDD + 0.3
V
2.5
DVDD + 0.3
CVDD + 0.3
DVDD + 0.3
X2/CLKIN
1.4
All other inputs
2.0
VIL
Low-level input voltage
RS, INTn, NMI, X2/CLKIN, BIO, BCLKR0,
BCLKR1, BCLKR2, BCLKX0, BCLKX1,
BCLKX2, HAS, HCS, HDS1, HDS2, TCK,
CLKMDn, DVDD = 3.3
All other inputs
0.3 V
–0.3
0.6
V
–0.3
0.8
IOH
IOL
TC
§Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be
designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
Excessive exposure to these conditions can adversely affect the long-term reliability of the devices. System-level concerns such as bus
contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as or prior
to the I/O buffers, and then powered down after the I/O buffers.
High-level output current
–300
μ
A
mA
°
C
Low-level output current
1.5
Operating case temperature
–40
100
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