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| 型號： | TLC34076-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（170MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 46/60頁 |
| 文件大小： | 408K |
| 代理商： | TLC34076-170 |
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3–5
3.6
Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
MHz
MHz
MHz
SCLK frequency (see Note 8)
VCLK frequency
Pixel data latching frequency (see Note 9)
85
85
110
ten1
tdis1
tv1
tPLH1
td1
Enable time, RD low to D<0:7> valid
40
ns
Disable time, RD high to D<0:7> disabled
17
ns
Valid time, D<0:7> valid after RD high
Propagation delay time, SFLAG/NFLAG
↑
to SCLK high (see Note 7)
Delay time, RD low to D<0:7> starting to turn on
5
ns
0
20
ns
5
ns
td2
Delay time, selected input clock high/low to DOTCLK (internal signal)
high/low
7
ns
td3
td4
td5
Delay time, DOTCLK high/low to VCLK high/low
6
ns
Delay time, VCLK high/low to SCLK high/low (see Note 10)
0
5
ns
Delay time, DOTCLK high/low to SCLK high/low
8
ns
td6
Delay time, DOTCLK high to IOR/IOG/IOB active (analog output delay
time) (seeNote11)
20
ns
td7
td8
tr
Analog output settling time(seeNote 12)
5
ns
Delay time, DOTCLK high to HSYNCOUT and VSYNCOUT valid
3
ns
Analog output rise time (see Note 13)
2
ns
Analog output skew
0
2
ns
NOTES:
7. This parameter applies when the split shift-register transfer (SSRT) function is enabled. See Section 2.9.1
for details.
8. SCLK can drive output capacitive loads up to 60 pF with worst-case transition time between the 10% and
90% levels less than 4 ns (typical 3 ns). SCLK can drive output capacitive loads up to 120 pF, with typical
transition time (10% to 90%) of 4 ns.
9. SCLK can be programmed to latch pixel data at the input port up to this limit. However, the SCLK output
buffer can only be used up to the SCLK frequency limit of 85 MHz.
10. VCLK frequency = SCLK frequency.
11. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.
12. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
±
1 LSB (settling time does not include clock and data feedthrough)
13. Measured between 10% and 90% of the full-scale transition
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