參數(shù)資料
型號(hào): TLC34076-170
廠商: Texas Instruments, Inc.
英文描述: Color-Palette(170MHz,與TLC34075兼容,另具24位和16位真彩色模式)
中文描述: 顏色調(diào)色板(170MHz的,與TLC34075兼容,另具24位和16位真彩色模式)
文件頁數(shù): 45/60頁
文件大?。?/td> 408K
代理商: TLC34076-170
3–4
3.5
Timing Requirements
MIN
MAX
UNIT
DOTCLK frequency
170
MHz
CLK0 frequency for VGA pass-through mode
85
MHz
tc
Clock cycle time
TTL
7.4
ns
ECL
5.8
tsu1
th1
tsu2
th2
Setup time, RS<0:3> valid before RD or WR
Hold time, RS<0:3> valid after RD or WR
Setup time, D<0:7> valid before WR
Hold time, D<0:7> valid after WR
Setup time, VGA<0:7> and HSYNC, VSYNC, and VGABLANK valid before
CLK0
Hold time, VGA<0:7> and HSYNC, VSYNC, and VGABLANK valid after CLK0
Setup time, P<0:31> valid before SCLK
Hold time, P<0:31> valid after SCLK
Setup time, HSYNC, VSYNC, and BLANK valid before VCLK
Hold time, HSYNC, VSYNC, and BLANK valid after VCLK
Pulse duration, RD or WR low
10
ns
10
ns
35
ns
0
ns
tsu3
2
ns
th3
tsu4
th4
tsu5
th5
tw1
tw2
2
ns
0
ns
5
ns
5
ns
2
ns
50
ns
Pulse duration, RD or WR high
30
ns
tw3
Pulse duration clock high
Pulse duration, clock high
TTL
3
ns
ECL
2.5
tw4
Pulse duration clock low
Pulse duration, clock low
TTL
3
ns
ECL
2.5
tw5
tw6
NOTES:
Pulse duration, SFLAG/NFLAG high (see Note 6)
30
ns
Pulse duration, SCLK high (see Note 7)
15
55
ns
5. TTL input signals are 0 to 3 V with less than 3-ns rise/fall time between the 10% and 90% levels unless
otherwise specified. ECL input signals are VDD–1.8 V to VDD–0.8 V with less than 2-ns rise/fall time
between the 20% and 80% levels. For input and output signals, timing reference points are at the 10% and
90% signal levels. Analog output loads are less than 10 pF. D<0:7> output loads are less than 50 pF. All
other output loads are less than 50 pF, unless otherwise specified.
6. This parameter applies when the split shift-register transfer (SSRT) function is enabled. See Section 2.9.1
for details.
7. This parameter applies when the split shift-register transfer (SSRT) function is enabled. See Section 2.9.1
for details.
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