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參數(shù)資料
| 型號： | TLC34076-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（170MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 408K |
| 代理商： | TLC34076-170 |
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1–6
1.5
Terminal Functions (Continued)
PIN
I/O
DESCRIPTION
NAME
NO.
31
RD
I
(TTL
compatible)
A low logic level on the read strobe input initiates a read from the
TLC34076-170 register map. Reads are performed asynchronously and
are initiated on the falling edge of RD (see Figure 3–1).
RS<0:3>
32–35
I
(TTL
compatible)
The register select inputs specify the location in the register map that is to
be accessed as shown in Table 2–1.
SCLK
79
O
(TTL
compatible)
The shift clock output is selected as a submultiple of the dot clock input.
SCLK is gated off during blanking.
SFLAG/
NFLAG
62
I
(TTL
compatible)
The split shift-register transfer flag or nibble flag input has two functions.
When the general control register bit 3 = 0 and bit 2 = 1, the split
shift-register transfer function is enabled and a low-to-high transition on
this terminal during a blank sequence initiates an extra SCLK cycle to allow
a split shift-register transfer in the VRAMs. When the general control
register bit 3 = 1 and bit 2 = 0, the special nibble mode is enabled and this
input is sampled at the falling edge of VCLK. A high sample value indicates
that the next SCLK rising edge should latch the high nibble of each byte
of the pixel data bus; a low sample value indicates that the low nibble of
each byte of the pixel data bus should be latched (see Section 2.9). When
the general control register bit 3 = 0 and bit 2 = 0, this terminal is ignored.
The condition of bit 3 = 1 and bit 2 = 1 is not allowed, and device operation
is unpredictable if the bits are set to these values.
VCLK
78
O
(TTL
compatible)
The video clock output is user-programmable, and it is used for the
synchronization of the TLC34076-170 to a graphics processor.
VDD
45, 55,
57, 81
I
All VDD terminals must be connected. The analog and digital VDD terminals
are connected internally.
VGA<0:7>
65–72
I(TTL
compatible)
The VGA pass-through bus can be selected as the pixel bus for VGA
pass-through mode. It does not allow for any multiplexing.
Vref
53
I
The voltage reference for the DACs. An internal voltage reference of
nominally 1.235 V is supplied. A 0.1-
μ
F ceramic capacitor between this
terminal and GND is recommended for noise filtering using either the
internal or an external reference voltage. The internal reference voltage
can be overridden by an externally supplied voltage. The typical
connection is shown in Appendix B.
WR
30
I
(TTL
compatible)
A low logic level on the write strobe input initiates a write to the
TLC34076-170 register map. Write transfers are asynchronous. The data
written to the register map is latched on the rising edge of WR (see
Figure 3–1).
8/6
64
I
(TTL
compatible)
The DAC resolution selection terminal selects the data bus width (eight or
six bits) for the DACs and is provided to maintain compatibility with the
INMOS IMSG176/8 color palette. When this terminal is at a high logic level,
8-bit bus transfers are used, with D<7> being the MSB and D<0> the LSB.
For 6-bit bus operation, while the color palette still has the 8-bit information,
D<5> shifts to the bit 7 position, D<0> shifts to the bit 2 position, and the
two LSBs are filled with zeros at the output MUX to the DAC. When read
in the 6-bit mode, the palette-holding register zeroes out the two MSBs.
Although leaving unused terminals floating does not adversely affect device operation, tying unused terminals to GND
lowers power consumption and thus is recommended.
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|---|---|
| TLC34076-85FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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