- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385929 > TLC34076-170 (Texas Instruments, Inc.) Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式) PDF資料下載
參數(shù)資料
| 型號(hào)： | TLC34076-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（170MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 34/60頁 |
| 文件大?。?/td> | 408K |
| 代理商： | TLC34076-170 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
PEDESTAL
7.5-IRE
0-IRE
2–17
The relationship between R
SET
and the full-scale output current IOG is:
R
SET
(
) = K1
×
V
REF
(V) / IOG (mA)
The full-scale output current on IOR and IOB for a given R
SET
is:
IOR, IOB (mA) = K2
×
V
REF
(V) / R
SET
(
)
where K1 and K2 are defined as:
IOG
IOR, IOB
8-BIT OUTPUT
K1 = 11,294
K1 = 10,684
6-BIT OUTPUT
K1 = 11,206
K1 = 10,600
8-BIT OUTPUT
K2 = 8,067
K2 = 7,462
6-BIT OUTPUT
K2 = 7,979
K2 = 7,374
2.8
For the normal modes, HSYNC and VSYNC are active (low) pulses and they are passed through
true/complement gates to the HSYNCOUT and VSYNCOUT outputs. The output polarities of HSYNCOUT
and VSYNCOUT can be programmed through the general control register. However, for the VGA
pass-through mode, the polarities needed for monitors are already provided at the feature connector from
which HSYNC and VSYNC are sourced so the TLC34076-170 passes HSYNC and VSYNC through to
HSYNCOUT and VSYNCOUT without polarity change. As described in Section 2.3 and Figures 2–2
through 2–5, the BLANK, HSYNC, and VSYNC inputs are sampled and latched on the falling edge of VCLK
in the normal modes, and they are latched on the rising edge of the CLK0 input in the VGA pass-through
mode. Refer to Figure 3–2 for the detailed timing.
HSYNC, VSYNC, and BLANK
The HSYNC and VSYNC inputs are used for both the VGA pass-through and normal modes. If the
application uses both VGA pass-through and normal modes, an external multiplexer is needed to select
HSYNC and VSYNC between VGA pass-through mode and normal mode. The MUXOUT signal is designed
for this purpose (see Sections 2.10 and 2.11).
The HSYNC, VSYNC, and BLANK signals have internal pipeline delays to align with the data at the DAC
outputs. Due to the sample and latch timing delay, it is possible to have active SCLK pulses after the BLANK
input becomes active. The relationship between VCLK and SCLK and the internal VCLK sample and latch
delay need to be carefully reviewed and programmed. See Section 2.3 and Figures 2–2 and 2–3 for more
details.
As shown in Figure 2–6 for the IOG DAC output, active HSYNC and VSYNC signals turn off the sync current
source (after the pipeline delay) independent of the BLANK signal level. In real applications, HSYNC and
VSYNC should only be active (low) when BLANK is active (low).
To alter the polarity of the HSYNCOUT and VSYNCOUT outputs in the normal modes, the MPU must set
or clear the corresponding bits in the general control register (see Section 2.11.1). Again, these two bits
affect only the normal modes, not the VGA pass-through mode. These bits default to 1.
2.9
2.9.1
The TLC34076-170 directly supports split shift-register transfer (SSRT) VRAMs. In order to allow the
VRAMs to perform a split shift-register transfer, an extra SCLK cycle must be inserted during the blank
sequence. This is initiated when the SSRT enable bit (bit 2 in the general control register) is set to 1, the
special nibble mode (SNM) bit (bit 3 in the general control register) is reset to 0 (see Section 2.11), and a
rising edge on the SFLAG/NFLAG input terminal is detected. An SCLK pulse is generated within 20 ns of
the rising edge of the SFLAG/NFLAG signal. A minimum 15-ns high logic level duration is provided to satisfy
all of the –15 VRAM requirements. By controlling the SFLAG/NFLAG rise time, the delay time from the rising
edge of the VRAM TRG signal to SCLK can be satisfied. The relationship between the SCLK,
SFLAG/NFLAG, and BLANK signals is shown in Figure 2–9.
Split Shift-Register Transfer VRAMs and Special Nibble Mode
Split Shift-Register Transfer VRAMs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC34076M-135 | Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| TLC4501(中文) | Self-Calibrating Dual Operational Amplifier(先進(jìn)LINEPIC，自校準(zhǔn)精密運(yùn)放) |
| TLC4502(中文) | Self-Calibrating Operational Amplifier(先進(jìn)LINEPIC，雙組自校準(zhǔn)精密運(yùn)放) |
| TLC540(中文) | 8-Bit Analog-To-Digital Converters With Serial Control And 11 Inputs(串行控制，75ksps,12通道，8位ADC) |
| TLC541(中文) | 8-Bit Analog-To-Digital Converters With Serial Control And 11 Inputs(串行控制，40ksps,12通道，8位ADC) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC34076-85FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC34077 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual |
| TLC34077135FN | 制造商:TI 功能描述:* |
| TLC352 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LinCMOSE DUAL DIFFERENTIAL COMPARATOR |
| TLC352CD | 功能描述:校驗(yàn)器 IC Dual Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。