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參數(shù)資料
| 型號： | TLC34076-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（170MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 22/60頁 |
| 文件大?。?/td> | 408K |
| 代理商： | TLC34076-170 |
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2–5
The trailing edge of VCLK is used internally by the TLC34076-170 to sample and latch the BLANK input.
When BLANK becomes active, SCLK is disabled as soon as possible. For example, if SCLK is high when
the sampled BLANK goes low, SCLK completes the clock cycle and returns to the low state. SCLK is then
held low until the sampled BLANK signal goes high. SCLK then is enabled to clock the VRAM again. The
TLC34076-170 video blanking circuitry is designed with sufficient pipeline delay to allow the internal
sampled BLANK signal to align with the pipelined RGB data to the video DACs. The logic described above
works in situations where the SCLK period is shorter than, equal to, or longer than the VCLK period.
When the VRAM split shift-register operation is performed (see Figure 2–3), the SCLK timing is adjusted
to work with the SFLAG input. The split shift-register operation inserts an SCLK during the BLANK period.
This causes the first group of pixel data to appear at the pixel port during the BLANK-active period. The first
SCLK after BLANK then latches this data into the TLC34076-170. Figure 2–3 shows the case when the split
shift-register transfer (SSRT) function is enabled. When a rising edge occurs on the SFLAG input, one SCLK
with a minimum 15-ns pulse duration is generated after the specified delay. This is designed to meet VRAM
timing requirements. The SSRT-generated SCLK replaces the first SCLK in the regular split shift-register
transfer as previously described. Refer to Section 2.9 for a detailed explanation of the SSRT function.
The default divide ratio for SCLK is 1:1 as used in mode 0 (see Table 2–6). Depending on the frequency
relationship between SCLK and VCLK, their phase relationship can be critical. Refer to Appendix C for a
more detailed explanation.
2.3.2
The VCLK frequency can be selected to be 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 of the dot clock frequency, or it
can be held at a high logic level. The default condition is for VCLK to be held at a high logic level. VCLK is
not used in VGA pass-through mode.
VCLK
VCLK is used by a GSP or custom-designed control logic to generate control signals (BLANK, HSYNC, and
VSYNC). As can be seen from Figures 2–2, 2–3, 2–4, and 2–5, the control signals sampled by VCLK are
enabled.
2nd
Group
SCLK
at P0–P31
Pixel Data
pipeline delay)
before DOTCLK
(internal signal
BLANK
for data latch)
(internal signal
LOAD
BLANK
VCLK
Group
1st
Last Group of Pixel Data
of Pixel Data
Latch Last Group
of Pixel Data
Latch First Group
of Pixel Data
Latch Last Group
3rd
Group
4th
Group
6th
Group
NOTE: Either the SSRT function is disabled (general control register bit 2 = 0), or the SFLAG/NFLAG input is held low
if the SSRT function is enabled (general control register bit 2 = 1).
Figure 2–2. SCLK/VCLK Control Timing (SSRT Disabled,
SCLK Frequency = VCLK Frequency)
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC34076-85FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC34077 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual |
| TLC34077135FN | 制造商:TI 功能描述:* |
| TLC352 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LinCMOSE DUAL DIFFERENTIAL COMPARATOR |
| TLC352CD | 功能描述:校驗(yàn)器 IC Dual Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
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