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參數(shù)資料
| 型號： | TLC34076-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（170MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 16/60頁 |
| 文件大?。?/td> | 408K |
| 代理商： | TLC34076-170 |
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1–5
1.5
Terminal Functions
PIN
I/O
DESCRIPTION
NAME
NO.
60, 61
BLANK,
VGABLANK
I
(TTL
compatible)
The two blanking inputs are provided to remove any external multiplexing
of the signals that may cause data and blank to skew. When the VGA
pass-through mode is set in the multiplex control register, the VGABLANK
input is used for blanking; otherwise, BLANK is used.
CLK<0:2>
77, 76, 75
I
(TTL
compatible)
The three dot-clock inputs can be used to drive the dot clock at frequencies
up to 135 MHz. When the VGA pass-through mode is active, CLK0 is used
by default.
CLK3, CLK3
74, 73
I
(TTL/ECL
compatible)
The dual-mode dot-clock inputs are ECL-compatible inputs, but a TTL
clock may be used on either CLK3 or CLK3 if so selected in the input clock
selection register. These inputs may be selected as the dot clocks for any
frequency of operation up to the device limit. One input can also be used
with a single-ended ECL clock source if the unused input is externally
terminated to provide the proper common-mode level.
COMP
52
I
The compensation input provides compensation for the internal reference
amplifier. A resistor (optional) and ceramic capacitor are required between
this terminal and VDD. The resistor and capacitor must be as close to the
device as possible to avoid noise pickup. Refer to Appendix B for more
details.
D<0:7>
36–43
I/O
(TTL
compatible)
The MPU interface data bus that is used to transfer data in and out of the
register map and palette/overlay RAM
FS ADJUST
51
I
The full-scale adjustment terminal must have a resistor connected
between it and GND to control the full-scale range of the DACs.
GND
44, 54,
56, 80
I
All GND terminals must be connected. The analog and digital GND
terminals are connected internally.
HSYNCOUT,
VSYNCOUT
46, 47
O
(TTL
compatible)
The horizontal and vertical sync outputs of the true/complement gate
mentioned in the HSYNC, VSYNC description below (see Section 2.8)
HSYNC,
VSYNC
58, 59
I
(TTL
compatible)
The horizontal and vertical sync inputs that are used to generate the sync
level on the green current output. They are active-low inputs for the normal
modes and are passed through a true/complement gate. For the VGA
pass-through mode, they are passed through to HSYNCOUT and
VSYNCOUT without polarity change as specified by the control register
(see Section 2.8).
These analog current outputs can drive a 37.5-
load directly (doubly
terminated 75-
line), thus eliminating the need for any external buffering.
IOR, IOG,
IOB
48, 49, 50
O
MUXOUT
63
O
(TTL
compatible)
The multiplex output control is software programmable. It is set low to
indicate to external devices that VGA pass-through mode is being used
when the multiplex control register value is set to 2Dh. If bit 7 of the general
control register is set high after the mode is set, this output goes high. This
terminal is only used for external control; it affects no internal circuitry.
P<0:31>
29–1,
84–82
I
(TTL
compatible)
The pixel input port can be used in various modes as shown in the multiplex
control register. It also supports little-/big-endian data formats. All unused
terminals must be tied to GND.
Although leaving unused terminals floating does not adversely affect device operation, tying unused terminals to GND
lowers power consumption and thus is recommended.
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