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參數(shù)資料
| 型號： | TLC34076-170 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（170MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 21/60頁 |
| 文件大?。?/td> | 408K |
| 代理商： | TLC34076-170 |
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SCLK
BITS
2. . . 0
divide DOTCLK by
divide
DOTCLK by
0
1
1
2
0
4
8
16
32
BITS
5. . .3
VCLK
2–4
Table 2–4. Output Clock Selection Register Format
BITS
3
0
1
0
1
0
1
X
X
X
X
X
X
X
X
g
e
d
e
FUNCTION
5
0
0
0
0
1
1
1
X
X
X
X
X
X
X
4
0
0
1
1
0
0
1
X
X
X
X
X
X
X
2
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
0
0
1
1
0
0
1
0
X
X
X
X
X
X
X
0
1
0
1
0
1
X
V
V
V
V
V
V
V
S
S
S
S
S
S
S
e
h
n
l
C
C
C
C
C
C
C
C
C
C
C
C
C
C
L
L
L
L
L
L
L
L
L
L
L
L
L
L
K
K
K
K
K
K
K
K
K
K
K
K
K
K
c
a
f
f
f
f
f
f
o
f
f
f
f
f
f
o
r
r
r
r
r
r
r
e
e
e
e
e
e
q
q
q
q
q
q
p
q
q
q
q
q
q
p
u
u
u
u
u
u
u
u
u
u
u
u
u
u
e
e
e
e
e
e
t
e
e
e
e
e
e
t
n
n
n
n
n
n
n
n
n
n
n
n
c
c
c
c
c
c
y
y
y
y
y
y
=
=
=
=
=
=
D
D
D
D
D
D
O
O
O
O
O
O
T
T
T
T
T
T
C
C
C
C
C
C
L
L
L
L
L
L
l
L
L
L
L
L
L
l
K
K
K
K
K
K
o
K
K
K
K
K
K
o
f
f
f
f
f
f
i
f
f
f
f
f
f
i
r
r
r
r
r
r
c
r
r
r
r
r
r
c
e
e
e
e
e
e
e
e
e
e
e
e
q
q
q
q
q
q
h
q
q
q
q
q
q
l
u
u
u
u
u
u
i
u
u
u
u
u
u
e
e
e
e
e
e
e
n
n
n
n
n
n
c
c
c
c
c
c
y
y
y
y
y
y
/
/
/
/
/
2
4
8
1
3
6
2
u
t
h
e
l
d
a
t
g
g
g
h
l
e
v
e
l
(
d
e
f
a
u
l
t
c
o
n
d
i
t
i
o
n
)
§
r
r
r
r
r
r
e
e
e
e
e
e
c
c
c
c
c
c
y
y
y
y
y
y
=
=
=
=
=
=
D
D
D
D
D
D
O
O
O
O
O
O
T
T
T
T
T
T
C
C
C
C
C
C
e
e
e
e
e
e
n
n
n
n
n
n
c
c
c
c
c
c
y
y
y
y
y
y
/
/
/
/
/
2
4
8
1
3
6
2
u
e
t
h
e
l
d
a
t
v
e
l
l
o
w
(
d
e
f
a
u
l
t
c
o
n
d
i
t
i
o
n
)
§
R
W
a
§T
e
h
n
h
i
s
t
r
b
i
t
s
6
a
n
d
7
a
o
r
e
i
d
o
n
’
t
b
i
t
s
.
n
t
e
n
i
c
n
e
l
o
.
c
k
s
e
l
e
c
t
i
n
s
a
l
t
e
r
e
d
,
a
m
i
n
i
m
u
m
3
0
-
n
s
d
e
l
a
y
i
s
i
n
c
u
r
r
e
d
b
e
f
o
r
e
t
h
e
n
e
w
c
l
o
c
k
s
a
r
e
s
t
a
b
i
l
i
z
e
d
s
r
u
i
g
s
e
n
i
n
d
i
c
a
t
e
t
h
e
p
o
w
e
r
-
u
p
c
o
n
d
i
t
i
o
n
s
r
e
q
u
i
r
e
d
t
o
s
u
p
p
o
r
t
t
h
e
V
G
A
p
a
s
s
-
t
h
r
o
u
g
h
m
o
d
e
.
T
(
a
b
u
l
e
p
u
2
t
–
5
.
V
c
C
k
L
K
/
S
l
C
L
K
D
i
v
i
d
e
R
a
t
i
o
S
e
l
e
c
t
i
o
n
O
t
C
l
o
S
e
e
c
t
i
o
n
R
e
g
i
s
t
e
r
V
a
l
u
e
i
n
H
e
x
)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
2
4
8
1
63
2
0
0
0
011
100
101
0
0
1
0
0
1
18
20
28
00
80
011
19
21
29
10
90
12
1A
22
2A
20
A0
13
1B
23
2B
30
B0
14
1C
24
2C
40
C0
15
1D
25
2D
5
D
Output clock selection register bits
2.3.1
SCLK
Data is latched inside the device on the rising edge of LOAD, which is the same as SCLK but not disabled
during the period when BLANK is active. Therefore, SCLK must be set as a function of the pixel bus width
and the number of bit planes. SCLK can be selected as divisions of 1, 2, 4, 8, 16, or 32 of the dot clock. If
SCLK is not used, the output is switched off and held low to protect against VRAM lock-up due to invalid
SCLK frequencies. SCLK is also held low during the period when BLANK is active. The SCLK control timing
has been designed to interface directly with the external system VRAM. The shift register in the system
VRAM should be updated during the period when BLANK is active. This allows the first SCLK after the period
when BLANK is active to clock the VRAM and enable the first group of pixel data to appear on the pixel bus,
as well as at the TLC34076-170 pixel input port. The second SCLK after the period when BLANK is active
latches the first group of pixel port data into the TLC34076-170 (see Figure 2–2).
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