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參數(shù)資料
| 型號(hào)： | THS8083T |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL |
| 中文描述： | 三8位，80 MSPS的，在3.3 V視頻和圖形數(shù)字轉(zhuǎn)換器與數(shù)字鎖相環(huán) |
| 文件頁數(shù)： | 51/61頁 |
| 文件大小： | 278K |
| 代理商： | THS8083T |
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5
–
7
5.4.9.2 Closed Loop
PARAMETER
f(HS)
t(acq)
TEST CONDITIONS
MIN
15
TYP
MAX
100
UNIT
kHz
HS locking range
Lock-in time
5
12
ms
t(JCS)
Short term jitter
Short-term jitter
See Note 16
700 (p-p)
185 (rms)
ps
TA = 25
°
C
1250 (p-p)
440 (rms)
ps
t(JCL)
Long term jitter
Long-term jitter
See Note 16
700 (pk-pk)
185 (rms)
ps
TA = 25
°
C
1250 (p-p)
440 (rms)
ps
NOTE 16: PLL characterization:
Short term jitter in open loop or closed loop is defined as the variation within one PLL update period (= within the same video line) of
the clock rising edge. This is measured visually by capturing the clock and displaying it on a digital scope with a persistency of one
video line. Numerically the time instants of the rising edges, at a defined voltage level, of a number of clock cycles (N = 800) are
captured at high sampling rate. From these time instants, the average clock time period is calculated. The deviation between each
actual time instant and the ideal, based on the average clock time period, is defined as a statistically distributed jitter value along
one line. This jitter is measured on both DATACLK1 and DTOCLK3 outputs.
Long term jitter in closed loop is defined as the variation over one video frame of the Nth clock rising edge on each line. This is
measured by capturing the time instant that a defined level on the rising edge of the Nth clock after HS is reached on each line. The
same principle for calculation is used as for short term jitter but now for one sample taken on every line and N = 800 lines.
5.4.10 Typical Plots (25
°
C and Measured for Standard VESA Graphics Formats)
NOTE:
The THS8083 is configured for each video mode with I
2
C register settings as specified
in application note
Using THS8083 for PC Graphics and Component Video Digitizing
.
500
600
700
800
900
1000
1100
1200
1300
1400
1500
0
20
40
60
80
100
30 MHz Full-Scale
Sine Input
60 kHz Full-Scale
Ramp Input
P
–
0
50
100
150
200
250
300
350
0
50
100
Total Analog
AVDD_CH1+AVDD_CH2_3
Total Digital
AVDD_REF
DVDD
AVDD_PLL
C
–
f
–
Frequency
–
MHz
CURRENT
vs
FREQUENCY
Figure 5
–
2. Power Consumption
DVDD_PLL
f
–
Frequency
–
MHz
POWER
vs
FREQUENCY
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