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參數(shù)資料
| 型號： | THS8083T |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL |
| 中文描述： | 三8位，80 MSPS的，在3.3 V視頻和圖形數(shù)字轉(zhuǎn)換器與數(shù)字鎖相環(huán) |
| 文件頁數(shù)： | 35/61頁 |
| 文件大?。?/td> | 278K |
| 代理商： | THS8083T |
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3
–
11
3.2.23 Register Name: DTO_INC_2
Subaddress: 16 (R)
DTO_INC23
MSB
LSB
DTO_INC22
DTO_INC21
DTO_INC20
DTO_INC19
DTO_INC18
DTO_INC17
DTO_INC16
DTOINC[23..16]:
See register DTO_INC_0
Default: (changed during operation)
3.2.24 Register Name: DTO_INC_3
Subaddress: 17 (R)
DTO_INC31
MSB
LSB
DTO_INC30
DTO_INC29
DTO_INC28
DTO_INC27
DTO_INC26
DTO_INC25
DTO_INC24
DTO_INC[31..24]:
See register DTO_INC_0.
Default: (changed during operation)
3.2.25 Register Name: DTO_INC_4
Subaddress: 18 (R)
X
MSB
LSB
X
X
X
X
X
X
DTO_INC32
DTO_INC32:
See register DTO_INC_0.
Default: (changed during operation)
3.2.26 Register Name: SYNC_DETECT
Subaddress: 19 (R)
X
MSB
LSB
X
X
X
X
X
X
NO_SYNC
NO_SYNC:
Sync detection on HS.
0 = HS present
1 = HS missing
Default: (changed during operation)
3.2.27 Register Name: CLP_CTRL
Subaddress: 20 (R/W)
MSB
LSB
CLPSEL
CLP1_EN
CLP1_RG
CLP2_EN
CLP2_RG
CLP3_EN
CLP3_RG
CLPSEL
Selects the clamp timing signal
0: internal clamp timing pulse is selected (default)
1: external clamp timing pulse is selected
CLP1_EN: Enables/disables clamping on Channel 1
1: enable (default)
0: disable
CLP1_RG:Sets the clamp range for Channel 1
1: middle range
0: bottom range (default)
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