參數(shù)資料
型號(hào)： THS8083T
廠商： Texas Instruments, Inc.
英文描述： Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL
中文描述： 三8位，80 MSPS的，在3.3 V視頻和圖形數(shù)字轉(zhuǎn)換器與數(shù)字鎖相環(huán)
文件頁數(shù)： 50/61頁
文件大小： 278K
代理商： THS8083T
5
–
6
5.4.8
Output Formatter/Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fclk
fclk
tsu(OUT)
th(OUT),
th(DHS)
tsu(DHS)
tPLH(OE)
tPHL(OE)
Maximum conversion rate
80
MHz
Minimum conversion rate
10
MHz
Setup time
3
ns
Hold time
With respect to 50% level of rising
edge on DATACLK
1
ns
Setup time
4
ns
Propagation (delay) time, low-to-high
See Note 13
8.5
ns
Propagation (delay) time, high-to-low-level output
8
DATACLK1 output duty cycle
40%
58%
HS and data pipeline delay
See Note 14
See timing diagrams
NOTES: 13. Output timing
–
OE timing tPLH(OE) is measured from the VIH(MIN) level of OE to the high-impedance state of the output data. The
digital output load is not higher than 10 pF.
OE iming PHL(OE) s measured rom he VIL(MAX) evel of OE o he nstant when he output data eaches VOH(min) or VOL(max) output
levels. The digital output load is not higher than 10 pF.
14. Pipeline delay (latency)
–
The number of clock cycles between conversion initiation on an input sample and the corresponding output
data being made available. Once the data pipeline is full, new valid output data are provided every clock cycle.
5.4.9
PLL
5.4.9.1 Open Loop
PARAMETER
TEST CONDITIONS
MIN
10
TYP
MAX
80
UNIT
MHz
DTO frequency range, f(DTO)
Instantaneous jitter, t(INS)
THS8083CPHP
260 (p-p)
ps
Short term jitter t
See Note 15
525 (p-p)
150 (rms)
ps
TA = 25
°
C
900 (p-p)
360 (rms)
ps
Phase Increment
11.25
Monotonic
deg
NOTE 15: PLL characterization:
Instantaneous jitter is the pk-pk variation of position of clock rising edge between succeeding periods.
Short term jitter in open loop or closed loop is defined as the variation within one PLL update period (= within the same video line) of
the clock rising edge. This can be measured visually by capturing the clock and displaying it on a digital scope with a persistency of
one video line. Numerically the time instants of the rising edges, at a defined voltage level, of a number N of clock cycles (N = 800)
are captured at high sampling rate. From these time instants, the average clock time period is calculated. The deviation between
each actual time instant and the ideal, based on the average clock time period, is defined as a statistically distributed jitter value
along one line. This jitter is measured on both DATACLK1 and DTOCLK3 outputs.
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