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參數(shù)資料
| 型號： | THS8083T |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL |
| 中文描述： | 三8位，80 MSPS的，在3.3 V視頻和圖形數(shù)字轉(zhuǎn)換器與數(shù)字鎖相環(huán) |
| 文件頁數(shù)： | 25/61頁 |
| 文件大小： | 278K |
| 代理商： | THS8083T |
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3
–
1
3 Register Definition
3.1
I
2
C Protocol
The THS8083 is a slave I
2
C device on which both write and read are supported. As shown in the register map, there
are some status control registers that can only be read.
The device can support FAST I
2
C mode (SCL up to 400 kHz) when the DTO clock is running at over 25 MHz; at lower
DTO frequencies only NORMAL I
2
C mode (SCL up to 100 kHz) is supported.
To discriminate between write and read operations, the device is addressed at separate device addresses. There is
an automatic internal subaddress increment counter to efficiently write/read multiple bytes in the register map during
one write/read operation. Furthermore, bit1 of the I
2
C device address is dependent upon the setting of the I2CA pin,
as follows:
If address selecting pin I2CA = 0, then
WRITE address is 40 hex (01000000)
READ address is 41 hex (01000001)
If address selecting pin I2CA = 1, then
WRITE address is 42 hex (01000010)
READ address is 43 hex (01000011)
3.1.1
Write Format
S
Slave address(w)
A
Sub-address
A
Data0
A
……
Data(N
–
1)
A
P
S
Slave address(w)
A
Start condition
0100000 (0x40) if I2CA=0 / 01000010 (0x42) if I2CA=1
Acknowledge, it is generated by THS8083
Subaddress
Data0
Data(N
–
1)
P
Subaddress of the 1
st
register to write, length: 1 byte
First byte of the data
Nth byte of the data
Stop condition
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