參數(shù)資料
型號(hào)： THS8083T
廠商： Texas Instruments, Inc.
英文描述： Triple 8-Bit, 80 MSPS, 3.3-V Video and Graphics Digitizer With Digital PLL
中文描述： 三8位，80 MSPS的，在3.3 V視頻和圖形數(shù)字轉(zhuǎn)換器與數(shù)字鎖相環(huán)
文件頁數(shù)： 48/61頁
文件大?。?/td> 278K
代理商： THS8083T
5
–
4
5.4.4
I
2
C Interface
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIL
VIH
f(SCL)
t(LOW)
t(HIGH)
th(DATA)
tsu(DATA)
C(b)
For DTO clock frequencies of minimum 25 MHz (I2C fast mode)
For DTO clock frequencies of below 25 MHz (I2C normal mode)
§
The device must internally provide a hold time of 300 ns for the SDA signal (referred to VIH(min) of the SCL signal) in order to bridge the undefined
region of the falling edge of SCL.
If the device is used in a standard mode I2C system the requirement of tsu(DATA)>=250 ns must be met.
#Cb= total capacitance of one bus line in pF
Low-level input voltage
0.99
V
High-level input voltage
2.31
V
SCL clock frequency
0
400
/100
kHz
μ
s
μ
s
μ
s
μ
s
pF
Low period of SCL
Valid for I2C fast mode support only.
See footnotes to SCL clock frequency.
1.3
High period of SCL
0.6
0
§
Data hold time
Data setup time
Capacitive load for each bus line#
100
400
5.4.5
ADC Channel
5.4.5.1 DC Accuracy
PARAMETER
TEST CONDITIONS
MIN
2 5
–
2.5
TYP
1 25
±
1.25
0 6/1
–
0.6/1
MAX
2 5
2.5
UNIT
LSB
Integral nonlinearity (INL)
PLL (see Note 7)
Differential nonlinearity (DNL)
No missing codes
Gain error
Offset error
Assured at nominal voltage supply levels only.
NOTES:
7. Integral nonlinearity (INL)
–
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full
scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond
the last code transition. The deviation is measured from the center of each particular code to the true straight line between these
two endpoints.
8. Differential nonlinearity (DNL)
–
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this
ideal value. Therefore, this measure indicates how uniform the transfer function step sizes are. The ideal step size is defined here
as the step size for the device under test (i.e., last transition level
–
first transition level)/(2n
–
2). Using this definition for DNL
separates the effects of gain and offset error. A DNL of less than
±
1 LSB ensures no missing codes. A DNL of less than
±
1/2 LSB
assures monotonic behavior.
9. Gain error
–
The first code transition should occur for an analog value 1/2 LSB above nominal negative full scale (the voltage applied
to the REFBI terminal). The last transition should occur for an analog value 1/2 LSB below nominal positive full scale (the voltage
applied to the REFTI terminal). Gain error is defined here as the deviation from the ideal location of the highest transition level on
the ADC transfer function.
10. Offset error
–
The first code transition should occur at a level 1/2 LSB above zero. Offset is defined as the deviation of the actual
first code transition from that point.
PLL (see Note 8)
1 75
1.75
LSB
–
1
Assured
ADC_INTREF (see Note 9)
ADC_INTREF (see Note 10)
20
–
20
mV
mV
5.4.5.2 Dynamic Performance
PARAMETER
TEST CONDITIONS
ADC_INTREF
MIN
TYP
MAX
UNIT
Effective number of bits, ENOB
fI = 20 MHz
fI = 20 MHz
fI = 1 MHz
fI = 1 MHz
(see Note 11)
6.4
Bits
Signal-to-total ratio without distortion, SNR
40.5
dB
Total harmonic distortion, THD
–
43.5
dB
Spurious free dynamic range, SFDR
49
dB
Analog input full-power bandwidth, BW
Based on analog input voltage of 1 dB FS referenced to the full-scale input range and a clock signal with 50% duty cycle.
500
MHz
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