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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 95/112頁 |
| 文件大小： | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
95
Lucent Technologies Inc.
Facility Data Links
(continued)
Facility Data Link Parameter/Status Registers
The facility data link (FDL) has eight registers summarized in the following table.
Table 100. Facility Data Link Registers
Access to the 64-bit FIFO is through register 07 (FDL_SR3).
The following registers define the mode configuration of each FDL, and are all read/write registers.
Table 101. FDL Configuration Control Register (FDL_PR0)
Register Name
FDL_PR0
FDL_PR1
FDL_PR2
FDL_PR3
FDL_SR0
FDL_SR1
FDL_SR2
FDL_SR3
Function
Parameter
Parameter
Parameter
Parameter
Status
Status
Status
Status
Address
0000
0001
0010
0011
0100
0101
0110
0111
Type
R/W
R/W
R/W
R/W
R
R
R
R
Bits
0
Description
FDL Receiver Reset (HRR).
HRR = 1 generates an internal pulse that resets the FDL receiver. The FDL
receiver FIFO and related circuitry are cleared. The REOF, RF, RIDLE, and OVERRUN status bits are
cleared. This bit resets to 0.
FDL Receiver Enable (HRE).
HRE = 1 activates the FDL receiver. HDLC is the default mode of opera-
tion. HRE = 0 forces the receiver into an inactive state. This bit resets to 0.
FDL Receive PRM Frames (HRPF).
HRPF = 1 allows the receive FDL unit to write the entire received
performance report message into the receive FIFO. This bit resets to 0.
Test FIFO (TR FIFO).
This bit is reserved for testing purposes and should be set to 0.
Number of ANSI Code Detect CNCD[0:3].
These bits define the number of times an ANSI code must be
received before the code is recognized and stored. Resets to the value 0101(10). A value of 1000(1) is
set when 0000 is inadvertently written for these bits.
1
2
3
4—7
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