參數(shù)資料
型號(hào)： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁(yè)數(shù)： 14/112頁(yè)
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
14
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
*
I
u
indicates an internal pull-up; I
d
indicates an internal pull-down.
Pin
Symbol
Type
*
Name/Description
29
XCLK
I
u
Reference Clock
.
The clock signal used for clock and data recovery and
jitter attenuation. This clock must be ungapped and free of jitter.
For CLKS = 0, a 16x clock (for DS1, XCLK = 24.704 MHz ± 100 ppm and for
CEPT, XCLK = 32.768 MHz ± 100 ppm).
For CLKS = 1, a 1x clock (for DS1, XCLK = 1.544 MHz ± 100 ppm and for
CEPT, XCLK = 2.048 MHz ± 100 ppm).
To meet TBR 12/13 jitter accommodation requirements, clock tolerances
must be reduced to ±20 ppm. An internal 100 k
pull-up is on this pin.
Blue Clock
.
Input clock signal used to transmit the AIS signal (all 1s data
pattern). In DS1 mode, this clock is 1.544 MHz ± 32 ppm, and in CEPT mode,
this clock is 2.048 MHz ± 50 ppm. An internal 100 k
pull-up is on this pin.
Loss of XCLK
.
This pin is asserted high when the XCLK signal (pin 29) is
not present.
30
BCLK
I
u
31
LOXC
O
32
RESET
I
u
Hardware Reset (Active-Low)
.
If
RESET
is forced low, all internal states in
the line interface paths are reset and data flow through each channel will be
momentarily disrupted. The
RESET
pin must be held low for a minimum of
10 μs. An internal 50 k
pull-up is on this pin.
In-Circuit Test Control (Active-Low)
.
If
ICT
is forced low, certain output pins
are placed in a high-impedance state. Which output pins are affected is
controlled by the ICTMODE bit (register 4, bit 3). An internal 50 k
pull-up is
on this pin.
33
ICT
I
u
69—76
AD7—AD0
I/O
Microprocessor Interface Address/Data Bus.
If MPMUX = 0 (pin 20),
these pins become the bidirectional, 3-statable data bus. If MPMUX = 1,
these pins become the multiplexed address/data bus. In this mode, only the
lower 4 bits (AD[3:0]) are used for the internal register addresses.
79—82
A3—A0
I
Microprocessor Interface Address.
If MPMUX = 0 (pin 20), these pins
become the address bus for the microprocessor interface registers. If
MPMUX = 1 (pin 20) and CS = 0 (pin 24), A3 (pin 79) can be externally tied
high to use the internal chip selection function. The state of A[2:0] determines
the address of the device. The device is addressed when the state of pins
AD[6:4] matches the device address of A[2:0]. If this function is not used,
A[3:0] must be externally tied low.
83
MPCLK
I
Microprocessor Interface Clock.
Microprocessor interface clock rates from
twice the frequency of the line clock (3.088 MHz for DS1 operation,
4.096 MHz for CEPT operation) to 16.384 MHz are supported.
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