參數(shù)資料
型號: T7698
廠商: Lineage Power
英文描述: Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述: 四T1/E1線路接口和八路的T1/E1監(jiān)視器(四個T1/E1線接口和八T1/E1的監(jiān)控器)
文件頁數(shù): 73/112頁
文件大小: 1359K
代理商: T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
73
Lucent Technologies Inc.
Frame Monitors
(continued)
Frame Monitor Register Structure
T7698 frame monitor registers are structured into two groups:
1. Parameter registers (Framer_PR0—Framer_PR12, Framer_PR14).
2. Status and counter registers (accessed through register 15).
A. Clear-on-read status registers (Framer_SR0—Framer_SR7 and Framer_SR52).
B. Clear-on-read counter registers (Framer_SR8—Framer_SR51).
All status and counter registers are clocked with the receive frame monitor corresponding line clock
(TCLK1—TCLK4 and RCLK1—RCLK4 for the eight receive frame monitors).
All status registers are cleared on read. However, if the event or condition setting the status bit high is still present
at the time of the read, the bit will remain in the high state for the duration of the alarm condition. If the event or con-
dition is no longer present at the time of the read, then the bit is cleared on read. Moreover, only those bits in the 1
state at the time of the read are cleared.
All of the 16-bit counter registers are cleared on read only after reading both bytes. Once a read is initiated on the
byte, the updating of the counter is disabled until both bytes are read.
Table 48 summarizes the frame monitor registers.
Table 48. Frame Monitor Registers
Note: Register 13 is the global index register.
Register Name
Framer_PR0
Framer_PR1
Framer_PR2
Framer_PR3
Framer_PR4
Framer_PR5
Framer_PR6
Framer_PR7
Framer_PR8
Framer_PR9
Framer_PR10
Framer_PR11
Framer_PR12
Framer_PR14
Framer_SR
Function
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Parameter/Control
Status/Counter registers
Framer_SR0—Framer_SR52
are read through this register
Address
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1110
1111
Type
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read only
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