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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 91/112頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
91
Lucent Technologies Inc.
Facility Data Links
(continued)
FDL Features
ANSI T1.403 Bit Codes
1.
2.
The receive FDL monitor will detect any of the ANSI T1.403 ESF bit-oriented messages.
The received ESF FDL bit messages are received in the form 0X
5
X
4
X
3
X
2
X
1
X
0
011111111. The right-most bit is
received first. The bits designated as X are the defined ANSI ESF FDL code bits. These code bits are written in
the received FDL ANSI bit code status register (FDL_SR2) when the entire code is received.
The minimum number of times a valid code must be received before it is reported can be programmed from 1
to 10.
3.
The FDL ANSI Bit Code Status Register has the following format.
Table 96. FDL ANSI Bit Code Status Register (FDL_SR2)
ANSI Performance Report Messages (PRM)
As defined in ANSI T1.403, the Performance Report Messages consist of four pairs of octets containing receive
frame monitor status. The format of the PRM is shown in Table 97.
Table 97. Performance Report Message Structure
Note:
Octet numbering is as given in Figure 6 of ANSI T1.403-1995.
B7
0
B6
0
B5
X
5
B4
X
4
B3
X
3
B2
X
2
B1
X
1
B0
X
0
Octet
No.
5
6
7
8
9
10
11
12
PRM B7
PRM B6
PRM B5
PRM B4
PRM B3
PRM B2
PRM B1
PRM B0
G3
FE
G3
FE
G3
FE
G3
FE
LV
SE
LV
SE
LV
SE
LV
SE
G4
LB
G4
LB
G4
LB
G4
LB
U1
G1
U1
G1
U1
G1
U1
G1
U2
R
U2
R
U2
R
U2
R
G5
G2
G5
G2
G5
G2
G5
G2
SL
Nm
SL
Nm
SL
Nm
SL
Nm
G6
Nl
G6
Nl
G6
Nl
G6
Nl
t0
t1
t2
t3
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