參數(shù)資料
型號(hào)： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁(yè)數(shù)： 94/112頁(yè)
文件大小： 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
94
Lucent Technologies Inc.
Facility Data Links
(continued)
FDL Features
(continued)
Bit 6 of the SF byte is the abort status. A high (1) indicates the frame associated with this status byte was aborted
(i.e., the abort sequence was detected after an opening flag and before a subsequent closing flag). An abort can
also cause bits 7 and/or 4 to go high (1). An abort is not reported when a flag is followed by seven 1s.
If the FIFO overrun bit (bit 5) is high, it indicates that a FIFO overrun occurred (the 64-byte FIFO size was
exceeded; see the Receiver Overrun section below).
The bad byte count bit (bit 4) indicates whether or not the bit count received was a multiple of eight (i.e., an integer
number of bytes). A high (1) indicates that the bit count received after 0-bit deletion was not a multiple of eight, and
a low indicates that the bit count was a multiple of eight. When a non-byte-aligned frame is received, all bits
received are present in the receive FIFO, but the byte before the SF byte contains less than eight valid data bits.
The nondata bits are the first bits of the received CRC. The HDLC block provides no indication of how many of the
bits in the byte are valid. It is up to the user and the protocol to decide what to do with non-byte-aligned frames.
Bits 0 to 3 of the SF byte are not used and are guaranteed to be 0 when read. A good frame is implied when the SF
byte is 00 hexadecimal.
The last byte of a completed frame in the receive FIFO is always the SF byte. As a frame is received, the 2 bytes
preceding the closing flag are assumed to be the frame check sequence (CRC) bits and are not loaded into the
FIFO, unless the HRPF bit (register FDL_PR0, bit 2) is set. Thus, the final 2 bytes received in an aborted frame are
not placed in the queue, and an aborted frame of 2 bytes or less may cause only an SF status byte to appear in the
FIFO. The writing of the SF byte is followed by setting the REOF status bit (register FDL_SR0, bit 1).
The receive queue status (RQS) bits (register FDL_SR1, bits 0—6) are updated as bytes are loaded into the
receive FIFO. The SF byte is included in the byte count. When the first SF byte is placed in the FIFO, the EOF bit
(register FDL_SR1, bit 7) is set, and the status freezes until the FIFO is read. As bytes are read from the FIFO, the
RQS count decreases until it reads 1. The byte read when RQS is 0000001 and the EOF bit is high (1) is the SF
byte describing the error status of the frame just read. Once the first SF byte is read from the FIFO, the FIFO status
is updated to report the number of bytes to the next SF byte, if any, or the number of additional bytes present. When
EOF is low, no SF byte is currently present in the FIFO, and the RQS bits report the number of bytes present. As
bytes are read from the FIFO, RQS count decreases with each read until it reads 0 when the FIFO is totally empty.
The EOF bit is also low when the FIFO is completely empty. Thus, the RQS and EOF bits provide a mechanism to
recognize the end of one frame and the beginning of another. Reading the receiver status register does not affect
the FIFO buffers. In the event of a receiver overrun (see below), an SF byte is written to the receive FIFO. Multiple
SF bytes can be present in the FIFO. Note that the RQS reports only the number of bytes to the first SF status byte.
To allow users to tailor receiver FIFO service intervals to their systems, the receiver fill level (RFL) bits (register
FDL_PR1, bits 0—5) are provided. These bits are coded in binary and determine when the receiver full (RF) status
bit (register FDL_SR0, bit 1) is set. The value programmed in the RFL bits represents the total number of bytes
necessary in the FIFO to set the RF status bit. The RF bit alone is not sufficient to determine the number of bytes
to read, as some of the bytes may be SF bytes. The RQS and EOF bits allow the user to determine the number of
bytes to read.
Programming Note:
Since the receiver writing to the receive FIFO and the host reading from the receive FIFO are
asynchronous events, it is possible for a host read to put the number of bytes in the receive FIFO just below the
programmed RFL level and a receiver write to put it back above the RFL level. This causes the receiver full (RF)
status bit to be set again.
Receiver Overrun.
A receiver overrun occurs if the 64-byte limit of the receiver FIFO is exceeded, i.e., data has
been received faster than it has been read out of the receive FIFO and written to the system memory. Upon over-
run, an SF byte with the overrun bit (bit 5) set replaces the last byte in the FIFO. The SF byte can have other error
conditions present. For example, it is unlikely that the CRC is correct. Thus, care should be taken to prioritize the
possible frame errors in the software service routine. The last byte in the FIFO is overwritten with the SF byte
regardless of the type of byte (data or SF status) being overwritten. The overrun condition is reported by setting the
ROVERUN (register FDL_SR0, bit 2) status bit. Data is ignored until the condition is cleared and a new frame
begins. The overrun condition is cleared by reading register FDL_SR0 and reading at least one byte from the
receive FIFO. Because multiple frames can be present in the FIFO, good frames as well as the overrun frame can
be present. The host can determine the overrun frame by looking at the SF status byte.
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