參數(shù)資料
型號(hào): STR912FAW32H6T
廠(chǎng)商: 意法半導(dǎo)體
英文描述: ARM966E-S⑩ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA
中文描述: ARM966E -虜⑩16/32位閃存微控制器與以太網(wǎng),USB,加拿大,交流電機(jī)控制,4個(gè)定時(shí)器,模數(shù)轉(zhuǎn)換器,RTC和DMA的
文件頁(yè)數(shù): 30/99頁(yè)
文件大?。?/td> 979K
代理商: STR912FAW32H6T
Functional overview
STR91xFAx32 STR91xFAx42 STR91xFAx44
30/99
3.17
Ethernet MAC interface with DMA
STR91xFA devices in 128-pin and 144-ball packages provide an IEEE-802.3-2002
compliant Media Access Controller (MAC) for Ethernet LAN communications through an
industry standard Medium Independent Interface (MII). The STR91xFA requires an external
Ethernet physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the STR91xFA MII port using as many as 18 signals
(see pins which have signal names MII_* in
Table 9
).
The MAC corresponds to the OSI Data Link layer and the PHY corresponds to the OSI
Physical layer. The STR91xFA MAC is responsible for:
Data encapsulation, including frame assembly before transmission, and frame
parsing/error detection during and after reception.
Media access control, including initiation of frame transmission and recover from
transmission failure.
The STR91xFA MAC includes the following features:
Supports 10 and 100 Mbps rates
Tagged MAC frame support (VLAN support)
Half duplex (CSMA/CD) and full duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and group
addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. Transmit FIFO depth is 4 words
(32 bits each), and the receive FIFO is 16 words deep.
A 32-bit burst DMA channel residing on the AHB is dedicated to the Ethernet MAC for high-
speed data transfers, side-stepping the CPU for minimal CPU impact during transfers. This
DMA channel includes the following features:
Direct SRAM to MAC transfers of transmit frames with the related status, by descriptor
chain
Direct MAC to SRAM transfers of receive frames with the related status, by descriptor
chain
Open and Closed descriptor chain management
3.18
USB 2.0 slave device interface with DMA
The STR91xFA provides a USB slave controller that implements both the OSI Physical and
Data Link layers for direct bus connection by an external USB host on pins USBDP and
USBPN. The USB interface detects token packets, handles data transmission and
reception, and processes handshake packets as required by the USB 2.0 standard.
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STR912FAW34X6T 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:ARM966E-S⑩ 16/32-Bit Flash MCU with Ethernet, USB, CAN, AC motor control, 4 timers, ADC, RTC, DMA