參數(shù)資料
型號(hào)： STPCE1
英文描述： STPC ELITE DATASHEET / X86 CORE GENERAL PURPOSE PC COMPATIBLE SYSTEM ON CHIP
中文描述： STPC精英部件/ x86內(nèi)核PC兼容的通用目的片上系統(tǒng)
文件頁(yè)數(shù)： 84/87頁(yè)
文件大?。?/td> 1356K
代理商： STPCE1
DESIGN GUIDELINES
84/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Release 1.3 - January 29, 2002
6
PCI clocks
Measure PCICLKO:
- maximum is 33MHz by standard
- check it is at selected frequency
- it is generated from HCLK by a division
(1/2, 1/3 or 1/4)
Check PCICLKI equals PCICLKO
Verify PCICLKO loops to PCICLKI.
Verify maximum skew between any PCI clock
branch is below 2ns.
In Synchronous mode, check MCLKI.
7
Memory
clocks
Measure MCLKO:
- use a low-capacitance probe
- maximum is 100MHz
- check it is at selected frequency
- In SYNC mode MCLK=HCLK
- in ASYNC mode, default is 66MHz
Check MCLKI equals MCLKO
Verify load on MCLKI.
Verify MCLK programming (BIOS setting).
4
SYSRSTO#
Measure SYSRSTO# of STPC
See
Figure 4-3
for waveforms.
Verify SYSRSTI# duration.
Verify SYSRSTI# has no glitch
Verify clocks are running.
8a
PCI cycles
Check PCI signals are toggling:
- FRAME#, IRDY#, TRDY#, DEVSEL#
- these signals are active low.
Check, with a logic analyzer, that first
PCI cycles are the expected ones:
memory read starting at address with
lower bits to 0xFFF0
Verify PCI slots
If the STPC don’t boot
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
- ensure CMOS is cleared.
9a
ISA
cycles
to
boot memory
Check RMRTCCS# & MEMRD#
Check directly on boot memory pin
Verify MEMCS16#:
- must not be asserted for 8-bit memory
Verify IOCHRDY is not be asserted
Verify ISAOE# pin:
- it controls IDE / ISA bus demultiplexing
8b
Local Bus
cycles
to
boot memory
Check FCS0# & PRD#
Check directly on boot memory pin
Verify HCLK speed and CPU clock mode.
9b
Check, with a logic analyzer, that first
Local Bus cycles are the expected one:
memory read starting at the top of boot
memory less 16 bytes
If the STPC don’t boot
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
- ensure CMOS is cleared.
10
The CPU fills its first cache line by fetching 16 bytes from boot memory.
Then, first instructions are executed from the CPU.
Any boot memory access done after the first 16 bytes are due to the instructions executed by the CPU
=> Minimum hardware is correctly set, CPU executes code.
Please have a look to the Bios Writer’s Guide or Programming Manual to go further with your board testing.
Check:
How
Troubleshooting
相關(guān)PDF資料
PDF描述
STPCE1DDBC Microprocessor
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STPCELITE X86 Core General Purpose PC Compatible System - on - Chip
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
STPCE1DDBC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
STPCE1DDBI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
STPCE1EDBC 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core General Purpose PC Compatible System - on - Chip
STPCE1EDBI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:X86 Core General Purpose PC Compatible System - on - Chip
STPCE1EEBC 制造商:STMicroelectronics 功能描述:X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP - Bulk
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