參數(shù)資料
型號(hào): STPCE1
英文描述: STPC ELITE DATASHEET / X86 CORE GENERAL PURPOSE PC COMPATIBLE SYSTEM ON CHIP
中文描述: STPC精英部件/ x86內(nèi)核PC兼容的通用目的片上系統(tǒng)
文件頁(yè)數(shù): 13/87頁(yè)
文件大小: 1356K
代理商: STPCE1
PIN DESCRIPTION
Release 1.3 - January 29, 2002
13/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ISA_CLK
O
BT8TRP_TC
ISA Clock Output - Multiplexer Select
Line For IPC
ISA Clock x2 Output - Multiplexer Select
Line For IPC
Buffered 14MHz clock
Unlatched Address
Latched Address
Data Bus
Address Latch Enable
Memory Read and Memory Write
System Memory Read and Memory
Write
I/O Read and Write
Memory/IO Chip Select16
System Bus High Enable
Zero Wait State
Refresh Cycle.
Add On Card Owns Bus
Address Enable
I/O Channel Check.
I/O Channel Ready (ISA) - Busy/Ready
(IDE)
ISA/IDE Selection
General Purpose Chip Select
Time-Multiplexed Interrupt Request
Time-Multiplexed DMA Request
Encoded DMA Acknowledge
ISA Terminal Count
Real Time Clock Address Strobe
ROM/RTC Chip Select
Keyboard Chip Select
RTC Read/Write
RTC Data Strobe
1
ISA_CLK2X
O
BT8TRP_TC
1
OSC14M
LA[23:17]
SA[19:0]
SD[15:0]
ALE
MEMR#, MEMW#
O
O
I/O
I/O
O
I/O
BD8STRP_FT
BD8STRUP_FT
BD8STRUP_FT
BD8STRP_FT
BD4STRP_FT
BD8STRUP_FT
1
7
20
16
1
2
SMEMR#, SMEMW#
O
BD8STRUP_FT
2
IOR#, IOW#
MCS16#, IOCS16#
BHE#
ZWS#
REF#
MASTER#
AEN
IOCHCK#
I/O
I
O
I
O
I
O
I
BD8STRUP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD8STRP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRUP_FT
2
2
1
1
1
1
1
1
IOCHRDY
I/O
BD8STRUP_FT
1
ISAOE#
GPIOCS#
IRQ_MUX[3:0]
DREQ_MUX[1:0]
DACK_ENC[2:0]
TC
RTCAS
RMRTCCS#
KBCS#
RTCRW#
RTCDS#
O
I/O
I
I
O
O
O
I/O
I/O
I/O
I/O
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
1
1
4
2
3
1
1
1
1
1
1
LOCAL BUS
PA[23:20], [15], [8], [3:0]
PA[19:16], [14:12],[7:4]
PA[11]
PA[10:9]
PD[15:0]
PRD1#,PRD0#
PWR1#
PWR0#
PRDY
FCS1#, FCS0#
IOCS#[3]
IOCS#[2:0]
Note
1
: These pins must be connected to the 2.5 V
power supply. They
must not
be connected to the 3.3V supply.
Note
2
: See
Table 2-3
for buffer type descriptions.
O
O
O
O
I/O
O
O
O
I
O
O
O
BD4STRP_FT
BD8STRUP_FT
BD8STRP_FT
BD4STRUP_FT
BD8STRP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD4STRP_FT
BD8STRUP_FT
Address Bus
Address Bus
Address Bus
Address Bus
Data Bus
Peripheral Read Control
Peripheral Write Control
Peripheral Write Control
Data Ready
Flash Chip Select
I/O Chip Select
I/O Chip Select
10
11
1
2
16
2
1
1
1
2
1
3
Table 2-2. Definition of Signal Pins
Signal Name
Dir
Buffer Type
2
Description
Qty
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