參數(shù)資料
型號(hào)： STPCE1
英文描述： STPC ELITE DATASHEET / X86 CORE GENERAL PURPOSE PC COMPATIBLE SYSTEM ON CHIP
中文描述： STPC精英部件/ x86內(nèi)核PC兼容的通用目的片上系統(tǒng)
文件頁(yè)數(shù)： 45/87頁(yè)
文件大?。?/td> 1356K
代理商： STPCE1
ELECTRICAL SPECIFICATIONS
Release 1.3 - January 29, 2002
45/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
24
IOR#, IOW# asserted before SA[19:0]
24o
I/O access to 16-bit ISA Slave Standard cycle
24r
I/O access to 16-bit ISA Slave Standard cycle
MEMR#, MEMW# asserted before next ALE# asserted
25b
Memory access to 16-bit ISA Slave Standard cycle
25d
Memory access to 8-bit ISA Slave Standard cycle
SMEMR#, SMEMW# asserted before next ALE# asserted
25e
Memory access to 16-bit ISA Slave - 2BCLK
25f
Memory access to 16-bit ISA Slave Standard cycle
25h
Memory access to 8-bit ISA Slave Standard cycle
IOR#, IOW# asserted before next ALE# asserted
25i
I/O access to 16-bit ISA Slave Standard cycle
25k
I/O access to 16-bit ISA Slave Standard cycle
MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted
26b
Memory access to 16-bit ISA Slave Standard cycle
26d
Memory access to 8-bit ISA Slave Standard cycle
SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted
26f
Memory access to 16-bit ISA Slave Standard cycle
26h
Memory access to 8-bit ISA Slave Standard cycle
IOR#, IOW# asserted before next IOR#, IOW# asserted
26i
I/O access to 16-bit ISA Slave Standard cycle
26k
I/O access to 8-bit ISA Slave Standard cycle
Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted
28a
Memory access to 16-bit ISA Slave
28b
Memory access to 8-bit ISA Slave
Any command negated to IOR#, IOW# asserted
28c
I/O access to ISA Slave
MEMR#, MEMW# negated before next ALE# asserted
SMEMR#, SMEMW# negated before next ALE# asserted
IOR#, IOW# negated before next ALE# asserted
LA[23:17] valid to IOCHRDY negated
33a
Memory access to 16-bit ISA Slave - 4 BCLK
33b
Memory access to 8-bit ISA Slave - 7 BCLK
LA[23:17] valid to read data valid
34b
Memory access to 16-bit ISA Slave Standard cycle
34e
Memory access to 8-bit ISA Slave Standard cycle
ALE# asserted to IOCHRDY# negated
37a
Memory access to 16-bit ISA Slave - 4 BCLK
37b
Memory access to 8-bit ISA Slave - 7 BCLK
37c
I/O access to 16-bit ISA Slave - 4 BCLK
37d
I/O access to 8-bit ISA Slave - 7 BCLK
ALE# asserted to read data valid
38b
Memory access to 16-bit ISA Slave Standard Cycle
38e
Memory access to 8-bit ISA Slave Standard Cycle
38h
I/O access to 16-bit ISA Slave Standard Cycle
38l
I/O access to 8-bit ISA Slave Standard Cycle
Note: The signal numbering refers to
Table 4-7
19T
19T
Cycles
Cycles
25
10T
10T
Cycles
Cycles
25
10T
10T
10T
Cycles
Cycles
Cycles
25
10T
10T
Cycles
Cycles
26
12T
12T
Cycles
Cycles
26
12T
12T
Cycles
Cycles
26
12T
12T
Cycles
Cycles
28
3T
3T
Cycles
Cycles
28
3T
1T
1T
1T
Cycles
Cycles
Cycles
Cycles
29a
29b
29c
33
8T
14T
Cycles
Cycles
34
8T
14T
Cycles
Cycles
37
6T
12T
6T
12T
Cycles
Cycles
Cycles
Cycles
38
4T
10T
4T
10T
Cycles
Cycles
Cycles
Cycles
Table 4-11. ISA Bus AC Timing
Name
Parameter
Min
Max
Units
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