參數(shù)資料
型號(hào)： STE10/100E
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128
封裝： 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128
文件頁(yè)數(shù)： 6/66頁(yè)
文件大?。?/td> 396K
代理商： STE10/100E
STE10/100A
14/66
CR49(offset = c4h), PMR1, Power Management Register 1.
31~16
---
reserved
15
PMEST
PME_Status. This bit is set whenever the STE10/100A detects
a wake-up event, regardless of the state of the PME-En bit.
Writing a “1” to this bit will clear it, causing the STE10/100A to
deassert PME# (if so enabled). Writing a “0” has no effect.
If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not support
PME# generation from D3cold), this bit is by default 0;
otherwise, PMEST is cleared upon power-up reset only and is
not modified by either hardware or software reset.
X
R/W1C*
14,13
DSCAL
Data_Scale. Indicates the scaling factor to be used when
interpreting the value of the Data register. This field is required
for any function that implements the Data register.
The STE10/100A does not support Data register and
Data_Scale.
00b
RO
12~9
DSEL
Data_Select. This four bit field is used to select which data is
to be reported through the Data register and Data_Scale field.
This field is required for any function that implements the Data
register.
The STE10/100A does not support Data_select.
0000b
R/W
8
PME_En
PME_En. When set, enables the STE10/100A to assert
PME#. When cleared, disables the PME# assertion.
If PSD3c (bit 31 of PMR0) is cleared (i.e. it does not support
PME# generation from D3cold), this bit is by default 0;
otherwise, PME_En is cleared upon power up reset only and is
not modified by either hardware or software reset.
X
R/W
7~2
---
reserved.
000000b
RO
1,0
PWRS
PowerState. This two bit field is used both to determine the
current power state of the STE10/100A and to place the
STE10/100A in a new power state. The definition of this field is
given below.
00b - D0
01b - D1
10b - D2
11b - D3hot
If software attempts to write an unsupported state to this field,
the write operation will complete normally on the bus, but the
data is discarded and no state change occurs.
00b
R/W
R/W1C*, Read Only and Write one cleared.
Table 4. Configuration Registers Descriptions
Bit #
Name
Descriptions
Default Val
RW Type
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