參數(shù)資料
型號： STE10/100E
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128
封裝： 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128
文件頁數(shù)： 5/66頁
文件大?。?/td> 396K
代理商： STE10/100E
13/66
STE10/100A
15~8
DS
Driver Space for implementation-specific purpose. Since this
area won’t be cleared upon software reset, an STE10/100A
driver can use this R/W area as user-specified storage.
0
R/W
7 ~ 0
---
reserved
CR32(offset = 80h), SIG - Signature of STE10/100A
31~16
DID
Device ID, the device ID number of the STE10/100A.
2774h
RO
15~0
VID
Vendor ID, the vendor ID number of STMicroelectronics
104Ah
RO
CR48(offset = c0h), PMR0, Power Management Register0.
31
30
29
28
27
PSD3c,
PSD3h,
PSD2,
PSD1,
PSD0
PME_Support.
The STE10/100A will assert PME# signal while in the D0, D1,
D2, D3hot and D3cold power state. The STE10/100A supports
Wake-up from the above five states. Bit 31 (support wake-up
from D3cold) is loaded from EEPROM after power-up or
hardware reset. To support the D3cold wake-up function, an
auxiliary power source will be sensed during reset by the
STE10/100A Vaux_detect pin. If sensed low, PSD3c will be set
to 0; if sensed high, and if D3CS (bit 31of CSR18) is set
(CSR18 bits 16~31 are recalled from EEPROM at reset), then
bit 31 will be set to 1.
X1111b
RO
26
D2S
D2_Support. The STE10/100A supports the D2 Power
Management State.
1RO
25
D1S
D1_Support. The STE10/100A supports the D1 Power
Management State.
1RO
24~22
AUXC
Aux Current. These three bits report the maximum 3.3Vaux
current requirements for STE10/100A chip. If bit 31 of PMR0 is
‘1’, the default value is 111b, meaning the STE10/100A needs
375 mA to support remote wake-up in D3cold power state.
Otherwise, the default value is 000b, meaning the STE10/100A
does not support remote wake-up from D3cold power state.
XXXb
RO
21
DSI
The Device Specific Initialization bit indicates whether any
special initialization of this function is required before the
generic class device driver is able to use it.
0: indicates that the function does not require a device-specific
initialization sequence following transition to the D0
uninitialized state.
0RO
20
---
Reserved.
19
PMEC
PME Clock. Indicates that the STE10/100A does not rely on
the presence of the PCI clock for PME# operation
0RO
18~16
VER
Version. The value of 010b indicates that the STE10/100A
complies with Revision 1.0a of the PCI Power Management
Interface Specification.
010b
RO
15~8
NIP
Next Item Pointer. This value is always 0h, indicating that there
are no additional items in the Capabilities List.
00h
RO
7~0
CAPID
Capability Identifier. This value is always 01h, indicating the
link list item as being the PCI Power Management Registers.
01h
RO
Table 4. Configuration Registers Descriptions
Bit #
Name
Descriptions
Default Val
RW Type
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