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參數(shù)資料
| 型號： | STE10/100E |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 37/66頁 |
| 文件大?。?/td> | 396K |
| 代理商： | STE10/100E |
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STE10/100A
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6.2 Network Packet Buffer Management
6.2.1 Descriptor Structure Types
During normal network transmit operations, the STE10/100A transfers the data packets from transmit buffers in
the host’s memory to the STE10/100A’s transmit FIFO. For receive operations, the STE10/100A transfers the
data packet from its receive FIFO to receive buffers in the host’s memory. The STE10/100A makes use of de-
scriptors, data structures which are built in host memory and contain pointers to the transmit and receive buffers
and maintain packet and frame parameters, status, and other information vital to controlling network operation.
There are two types of structures employed to group descriptors, the Ring and the Chain, both supported by
the STE10/100A and shown below. The selection of structure type is controlled by RCH (RDES1 bit 24) and
TCH (TDES1 bit 24).
The transmit and receive buffers reside in the host’s memory. Any buffer can contain either a complete or partial
packet. A buffer may not contain more than one packet.
s
Ring structure: There are two buffers per descriptor in the ring structure. Support receive early interrupt.
Figure 5. Ring structure of frame buffer
own
Data Buffer
Length 1
Data
Length 2
Buffer1 pointer
Buffer2 pointer
Length 2 Length 1
Descriptor
.
Descriptor Pointer
CSR3 or CSR4
End of Ring
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