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參數(shù)資料
| 型號： | STE10/100E |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP128 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 32/66頁 |
| 文件大?。?/td> | 396K |
| 代理商： | STE10/100E |
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STE10/100A
38/66
Table 10. Receive Descriptor Descriptions
Bit#
Name
Descriptions
RDES0
31
OWN
Own bit
1: indicates that newly received data can be put into this descriptor
0: Host has not yet processed the received data currently in this descriptor.
30-16
FL
Frame length, including CRC. This field is valid only in a frame’s last descriptor.
15
ES
Error summary. Logical OR of the following bits:
0: overflow
1: CRC error
6: late collision
7: frame too long
11: runt packet
14: descriptor error
This field is valid only in a frame’s last descriptor.
14
DE
Descriptor error. This bit is valid only in a frame’s last descriptor.
1: the current valid descriptor is unable to contain the packet being currently received. The
packet is truncated.
13-12
DT
Data type.
00: normal
01: MAC loop-back
10: Transceiver loop-back
11: remote loop-back
These bits are valid only in a frame’s last descriptor.
11
RF
Runt frame (packet length < 64 bytes). This bit is valid only in a frame’s last descriptor.
10
MF
Multicast frame. This bit is valid only in a frame’s last descriptor.
9
FS
First descriptor.
8
LS
Last descriptor.
7
TL
Packet Too Long (packet length > 1518 bytes). This bit is valid only in a frame’s last descriptor.
6
CS
Late collision. Set when collision is active after 64 bytes. This bit is valid only in a frame’s last
descriptor
5
FT
Frame type. This bit is valid only in a frame’s last descriptor.
0: 802.3 type
1: Ethernet type
4
RW
Receive watchdog (refer to CSR15, bit 4). This bit is valid only in a frame’s last descriptor.
3
reserved
Default = 0
2
DB
Dribble bit. This bit is valid only in a frame’s last descriptor
1: Packet length is not integer multiple of 8-bit.
1
CE
1: CRC error. This bit is valid only in a frame’s last descriptor
0
OF
1: Overflow. This bit is valid only in a frame’s last descriptor
RDES1
31~26
---
reserved
25
RER
Receive end of ring. Indicates this descriptor is last, return to base address of descriptor
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